DVASM Listing for Input File: /TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/examples/riscv-avltree/dvasmavlinsrem.asm
DVASM execution completed on: Wed Aug 30 22:33:50 EDT 2023
--- Log Start
Framework JAR file is [file:/TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/code-and-manuals/dvasm.v1-r0.1.jar]
User macro directory[1] is: [/TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/examples/riscv-avltree]
Architecture JAR file selected is [file:/TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/code-and-manuals/dvasm.v1-r0.1.jar]
No architecture extension used
Parse elapsed time is: 2620 milliseconds
Input parsing completed succesfully
Dependencies preprocessing completed successfully
Dependencies resolution completed successfully
Code generation completed with warnings
Dependencies resolution completed successfully
Code generation completed successfully
Code generation elapsed time is: 146 milliseconds
--- Log End
1 | //--------------------------------------------------------------------------------------------------
2 | //
3 | // @ CopyRight Roberti & Parau Enterprises, Inc. 2021-2023
4 | //
5 | // This work is licensed under the Creative Commons Attribution 4.0 International License.
6 | // To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/
7 | // or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.
8 | //
9 | //--------------------------------------------------------------------------------------------------
10 | //
11 | // This code provides two entry points, one two insert a node into an AVL tree,
12 | // the other to remove a node
13 | //
14 | // In this example a node is composed of a pointer to a null terminated string
15 | // The nodes are inserted so that during a in-order traversal the strings
16 | // appear in sorted order.
17 | //
18 | // The code is divided into two parts:
19 | //
20 | // 1. The in-line macro that compare two strings belonging to two nodes
21 | //
22 | // 2. The SECTION that contains the two entry points
23 | //
24 | //--------------------------------------------------------------------------------------------------
25 | //
26 | // Macro InsCompString compare the strings of two nodes
27 | //
28 | // It carry out the string comparison as the strcmp C function,
29 | // and branch to the correct labels passed to the macro base on
30 | // the comparison results
31 | //
32 | #MACRO
33 | //MACRO InsCompString Node1, Node2, GtLbl, EqLbl, WReg[4-32]
34 |
35 | var addr1= WReg[0];
36 | var addr2= WReg[1];
37 | var wreg0= WReg[2];
38 | var wreg1= WReg[3];
39 |
40 | \#Label LD #addr1, 24[#Node1] // Load string addr from node 1
41 | \ LD #addr2, 24[#Node2] // Load string addr from node 2
42 | \ WHILE // Start DO block
43 | \ LBU #wreg0, 0[#addr1] // Load first string byte
44 | \ LBU #wreg1, 0[#addr2] // Load second string byte
45 |
46 | \ IF (#wreg0 > #wreg1), GOTO, ID= #GtLbl // Done greater than
47 | \ IF (#wreg0 < #wreg1), BREAK // Done if less than
48 |
49 | \ IF ( #wreg1 == 0 ), GOTO, ID= #EqLbl // Equal condition with equal flag
50 |
51 | \ ADDI #addr1, 1 // Get next char address (string 1)
52 | \ ADDI #addr2, 1 // Get next char address (string 2)
53 | \ ENDWHILE
54 | #END
55 | //
56 | // Actual code starts here
57 | //
58 | SETENV "RISCV", "RV64I:a,c,d,m,n,zicsr,zifencei", "LP64D", "linux"
Architecture is................................. RISCV
Number of registers............................. 32
Register bit length (XLEN)...................... 64
Number of floating registers.................... 32
Floating register bit length (FLEN)............. 64
(A) atomic extension............................ Used
(C) two byte opCode encoding extension.......... Used
(M) integer multiply/divide extension........... Used
(N) user level interrupt extension.............. Used
(ZTSO) total store ordering..................... Not Used
(ZICSR) control/status registers extension...... Used
(ZIFENCEI) instruction fetch fence extension.... Used
ABI............................................. LP64D
Operating System................................ LINUX
59 | // Define the srchitecture
60 | //
[+][-] 61 | BaseDef // Include standdard definitions
Macro [BASEDEF] source location is [JAR: /arch/RISCV/macros/BaseDef.mac]
[+][-] 61.1 |BASEDEF FrameWorkDef // Include DVASM framework base definitions
Macro [FRAMEWORKDEF] source location is [JAR: /framework/macros/FrameWorkDef.mac]
61.1.1 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 TRUE EQU 1
61.1.2 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 FALSE EQU 0
61.1.3 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 YES EQU 1
61.1.4 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 NO EQU 0
61.1.5 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF FLOFLOAT 3.14159265358 3.14159265358979323846264338327950288419717 PI EQU 3.14159265358979323846264338327950288419716939937510582097494459230781640628620899
61.1.6 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF FLOFLOAT 2.71828182845 2.71828182845904523536028747135266249775725 NAPIER EQU 2.71828182845904523536028747135266249775724709369995957496696762772407663035354759
61.1.6 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid section types
61.1.8 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_SHT_PROGBITS EQU 1
61.1.9 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000007 ELF_SHT_NOTE EQU 7
61.1.10 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000008 ELF_SHT_NOBITS EQU 8
61.1.10 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid section attributes
61.1.12 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_SHF_WRITE EQU 1
61.1.13 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000002 ELF_SHF_ALLOC EQU 2
61.1.14 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000004 ELF_SHF_EXECINSTR EQU 4
61.1.14 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid symbol bindings
61.1.16 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 ELF_STB_LOCAL EQU 0
61.1.17 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_STB_GLOBAL EQU 1
61.1.18 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000002 ELF_STB_WEAK EQU 2
61.1.18 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid symbol types
61.1.20 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 ELF_STT_NOTYPE EQU 0
61.1.21 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_STT_OBJECT EQU 1
61.1.22 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000002 ELF_STT_FUNC EQU 2
61.1.23 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000003 ELF_STT_SECTION EQU 3
61.1.24 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000004 ELF_STT_FILE EQU 4
61.2 |BASEDEF //
61.3 |BASEDEF // Base register definitions "R" prefix
61.4 |BASEDEF //
61.5 |BASEDEF ABSABSOLUTE 00000000 r0 EQU 0
61.6 |BASEDEF ABSABSOLUTE 00000001 r1 EQU 1
61.7 |BASEDEF ABSABSOLUTE 00000002 r2 EQU 2
61.8 |BASEDEF ABSABSOLUTE 00000003 r3 EQU 3
61.9 |BASEDEF ABSABSOLUTE 00000004 r4 EQU 4
61.10 |BASEDEF ABSABSOLUTE 00000005 r5 EQU 5
61.11 |BASEDEF ABSABSOLUTE 00000006 r6 EQU 6
61.12 |BASEDEF ABSABSOLUTE 00000007 r7 EQU 7
61.13 |BASEDEF ABSABSOLUTE 00000008 r8 EQU 8
61.14 |BASEDEF ABSABSOLUTE 00000009 r9 EQU 9
61.15 |BASEDEF ABSABSOLUTE 0000000A r10 EQU 10
61.16 |BASEDEF ABSABSOLUTE 0000000B r11 EQU 11
61.17 |BASEDEF ABSABSOLUTE 0000000C r12 EQU 12
61.18 |BASEDEF ABSABSOLUTE 0000000D r13 EQU 13
61.19 |BASEDEF ABSABSOLUTE 0000000E r14 EQU 14
61.20 |BASEDEF ABSABSOLUTE 0000000F r15 EQU 15
61.21 |BASEDEF ABSABSOLUTE 00000010 r16 EQU 16
61.22 |BASEDEF ABSABSOLUTE 00000011 r17 EQU 17
61.23 |BASEDEF ABSABSOLUTE 00000012 r18 EQU 18
61.24 |BASEDEF ABSABSOLUTE 00000013 r19 EQU 19
61.25 |BASEDEF ABSABSOLUTE 00000014 r20 EQU 20
61.26 |BASEDEF ABSABSOLUTE 00000015 r21 EQU 21
61.27 |BASEDEF ABSABSOLUTE 00000016 r22 EQU 22
61.28 |BASEDEF ABSABSOLUTE 00000017 r23 EQU 23
61.29 |BASEDEF ABSABSOLUTE 00000018 r24 EQU 24
61.30 |BASEDEF ABSABSOLUTE 00000019 r25 EQU 25
61.31 |BASEDEF ABSABSOLUTE 0000001A r26 EQU 26
61.32 |BASEDEF ABSABSOLUTE 0000001B r27 EQU 27
61.33 |BASEDEF ABSABSOLUTE 0000001C r28 EQU 28
61.34 |BASEDEF ABSABSOLUTE 0000001D r29 EQU 29
61.35 |BASEDEF ABSABSOLUTE 0000001E r30 EQU 30
61.36 |BASEDEF ABSABSOLUTE 0000001F r31 EQU 31
61.37 |BASEDEF //
61.38 |BASEDEF // Base register definitions "X" prefix
61.39 |BASEDEF //
61.40 |BASEDEF ABSABSOLUTE 00000000 x0 EQU 0
61.41 |BASEDEF ABSABSOLUTE 00000001 x1 EQU 1
61.42 |BASEDEF ABSABSOLUTE 00000002 x2 EQU 2
61.43 |BASEDEF ABSABSOLUTE 00000003 x3 EQU 3
61.44 |BASEDEF ABSABSOLUTE 00000004 x4 EQU 4
61.45 |BASEDEF ABSABSOLUTE 00000005 x5 EQU 5
61.46 |BASEDEF ABSABSOLUTE 00000006 x6 EQU 6
61.47 |BASEDEF ABSABSOLUTE 00000007 x7 EQU 7
61.48 |BASEDEF ABSABSOLUTE 00000008 x8 EQU 8
61.49 |BASEDEF ABSABSOLUTE 00000009 x9 EQU 9
61.50 |BASEDEF ABSABSOLUTE 0000000A x10 EQU 10
61.51 |BASEDEF ABSABSOLUTE 0000000B x11 EQU 11
61.52 |BASEDEF ABSABSOLUTE 0000000C x12 EQU 12
61.53 |BASEDEF ABSABSOLUTE 0000000D x13 EQU 13
61.54 |BASEDEF ABSABSOLUTE 0000000E x14 EQU 14
61.55 |BASEDEF ABSABSOLUTE 0000000F x15 EQU 15
61.56 |BASEDEF ABSABSOLUTE 00000010 x16 EQU 16
61.57 |BASEDEF ABSABSOLUTE 00000011 x17 EQU 17
61.58 |BASEDEF ABSABSOLUTE 00000012 x18 EQU 18
61.59 |BASEDEF ABSABSOLUTE 00000013 x19 EQU 19
61.60 |BASEDEF ABSABSOLUTE 00000014 x20 EQU 20
61.61 |BASEDEF ABSABSOLUTE 00000015 x21 EQU 21
61.62 |BASEDEF ABSABSOLUTE 00000016 x22 EQU 22
61.63 |BASEDEF ABSABSOLUTE 00000017 x23 EQU 23
61.64 |BASEDEF ABSABSOLUTE 00000018 x24 EQU 24
61.65 |BASEDEF ABSABSOLUTE 00000019 x25 EQU 25
61.66 |BASEDEF ABSABSOLUTE 0000001A x26 EQU 26
61.67 |BASEDEF ABSABSOLUTE 0000001B x27 EQU 27
61.68 |BASEDEF ABSABSOLUTE 0000001C x28 EQU 28
61.69 |BASEDEF ABSABSOLUTE 0000001D x29 EQU 29
61.70 |BASEDEF ABSABSOLUTE 0000001E x30 EQU 30
61.71 |BASEDEF ABSABSOLUTE 0000001F x31 EQU 31
61.72 |BASEDEF //
61.73 |BASEDEF // Alternate ABI register definitions
61.74 |BASEDEF //
61.75 |BASEDEF ABSABSOLUTE 00000001 ra EQU 1
61.76 |BASEDEF ABSABSOLUTE 00000002 sp EQU 2
61.77 |BASEDEF ABSABSOLUTE 00000003 gp EQU 3
61.78 |BASEDEF ABSABSOLUTE 00000004 tp EQU 4
61.79 |BASEDEF ABSABSOLUTE 00000005 t0 EQU 5
61.80 |BASEDEF ABSABSOLUTE 00000006 t1 EQU 6
61.81 |BASEDEF ABSABSOLUTE 00000007 t2 EQU 7
61.82 |BASEDEF ABSABSOLUTE 00000008 s0 EQU 8
61.83 |BASEDEF ABSABSOLUTE 00000009 s1 EQU 9
61.84 |BASEDEF ABSABSOLUTE 0000000A a0 EQU 10
61.85 |BASEDEF ABSABSOLUTE 0000000B a1 EQU 11
61.86 |BASEDEF ABSABSOLUTE 0000000C a2 EQU 12
61.87 |BASEDEF ABSABSOLUTE 0000000D a3 EQU 13
61.88 |BASEDEF ABSABSOLUTE 0000000E a4 EQU 14
61.89 |BASEDEF ABSABSOLUTE 0000000F a5 EQU 15
61.90 |BASEDEF ABSABSOLUTE 00000010 a6 EQU 16
61.91 |BASEDEF ABSABSOLUTE 00000011 a7 EQU 17
61.92 |BASEDEF ABSABSOLUTE 00000012 s2 EQU 18
61.93 |BASEDEF ABSABSOLUTE 00000013 s3 EQU 19
61.94 |BASEDEF ABSABSOLUTE 00000014 s4 EQU 20
61.95 |BASEDEF ABSABSOLUTE 00000015 s5 EQU 21
61.96 |BASEDEF ABSABSOLUTE 00000016 s6 EQU 22
61.97 |BASEDEF ABSABSOLUTE 00000017 s7 EQU 23
61.98 |BASEDEF ABSABSOLUTE 00000018 s8 EQU 24
61.99 |BASEDEF ABSABSOLUTE 00000019 s9 EQU 25
61.100 |BASEDEF ABSABSOLUTE 0000001A s10 EQU 26
61.101 |BASEDEF ABSABSOLUTE 0000001B s11 EQU 27
61.102 |BASEDEF ABSABSOLUTE 0000001C t3 EQU 28
61.103 |BASEDEF ABSABSOLUTE 0000001D t4 EQU 29
61.104 |BASEDEF ABSABSOLUTE 0000001E t5 EQU 30
61.105 |BASEDEF ABSABSOLUTE 0000001F t6 EQU 31
61.106 |BASEDEF //
61.107 |BASEDEF // Floating register definitions
61.108 |BASEDEF //
61.109 |BASEDEF ABSABSOLUTE 00000000 f0 EQU 0
61.110 |BASEDEF ABSABSOLUTE 00000001 f1 EQU 1
61.111 |BASEDEF ABSABSOLUTE 00000002 f2 EQU 2
61.112 |BASEDEF ABSABSOLUTE 00000003 f3 EQU 3
61.113 |BASEDEF ABSABSOLUTE 00000004 f4 EQU 4
61.114 |BASEDEF ABSABSOLUTE 00000005 f5 EQU 5
61.115 |BASEDEF ABSABSOLUTE 00000006 f6 EQU 6
61.116 |BASEDEF ABSABSOLUTE 00000007 f7 EQU 7
61.117 |BASEDEF ABSABSOLUTE 00000008 f8 EQU 8
61.118 |BASEDEF ABSABSOLUTE 00000009 f9 EQU 9
61.119 |BASEDEF ABSABSOLUTE 0000000A f10 EQU 10
61.120 |BASEDEF ABSABSOLUTE 0000000B f11 EQU 11
61.121 |BASEDEF ABSABSOLUTE 0000000C f12 EQU 12
61.122 |BASEDEF ABSABSOLUTE 0000000D f13 EQU 13
61.123 |BASEDEF ABSABSOLUTE 0000000E f14 EQU 14
61.124 |BASEDEF ABSABSOLUTE 0000000F f15 EQU 15
61.125 |BASEDEF ABSABSOLUTE 00000010 f16 EQU 16
61.126 |BASEDEF ABSABSOLUTE 00000011 f17 EQU 17
61.127 |BASEDEF ABSABSOLUTE 00000012 f18 EQU 18
61.128 |BASEDEF ABSABSOLUTE 00000013 f19 EQU 19
61.129 |BASEDEF ABSABSOLUTE 00000014 f20 EQU 20
61.130 |BASEDEF ABSABSOLUTE 00000015 f21 EQU 21
61.131 |BASEDEF ABSABSOLUTE 00000016 f22 EQU 22
61.132 |BASEDEF ABSABSOLUTE 00000017 f23 EQU 23
61.133 |BASEDEF ABSABSOLUTE 00000018 f24 EQU 24
61.134 |BASEDEF ABSABSOLUTE 00000019 f25 EQU 25
61.135 |BASEDEF ABSABSOLUTE 0000001A f26 EQU 26
61.136 |BASEDEF ABSABSOLUTE 0000001B f27 EQU 27
61.137 |BASEDEF ABSABSOLUTE 0000001C f28 EQU 28
61.138 |BASEDEF ABSABSOLUTE 0000001D f29 EQU 29
61.139 |BASEDEF ABSABSOLUTE 0000001E f30 EQU 30
61.140 |BASEDEF ABSABSOLUTE 0000001F f31 EQU 31
61.141 |BASEDEF //
61.142 |BASEDEF // Alternate ABI floating register definitions
61.143 |BASEDEF //
61.144 |BASEDEF ABSABSOLUTE 00000000 ft0 EQU 0
61.145 |BASEDEF ABSABSOLUTE 00000001 ft1 EQU 1
61.146 |BASEDEF ABSABSOLUTE 00000002 ft2 EQU 2
61.147 |BASEDEF ABSABSOLUTE 00000003 ft3 EQU 3
61.148 |BASEDEF ABSABSOLUTE 00000004 ft4 EQU 4
61.149 |BASEDEF ABSABSOLUTE 00000005 ft5 EQU 5
61.150 |BASEDEF ABSABSOLUTE 00000006 ft6 EQU 6
61.151 |BASEDEF ABSABSOLUTE 00000007 ft7 EQU 7
61.152 |BASEDEF ABSABSOLUTE 00000008 fs0 EQU 8
61.153 |BASEDEF ABSABSOLUTE 00000009 fs1 EQU 9
61.154 |BASEDEF ABSABSOLUTE 0000000A fa0 EQU 10
61.155 |BASEDEF ABSABSOLUTE 0000000B fa1 EQU 11
61.156 |BASEDEF ABSABSOLUTE 0000000C fa2 EQU 12
61.157 |BASEDEF ABSABSOLUTE 0000000D fa3 EQU 13
61.158 |BASEDEF ABSABSOLUTE 0000000E fa4 EQU 14
61.159 |BASEDEF ABSABSOLUTE 0000000F fa5 EQU 15
61.160 |BASEDEF ABSABSOLUTE 00000010 fa6 EQU 16
61.161 |BASEDEF ABSABSOLUTE 00000011 fa7 EQU 17
61.162 |BASEDEF ABSABSOLUTE 00000012 fs2 EQU 18
61.163 |BASEDEF ABSABSOLUTE 00000013 fs3 EQU 19
61.164 |BASEDEF ABSABSOLUTE 00000014 fs4 EQU 20
61.165 |BASEDEF ABSABSOLUTE 00000015 fs5 EQU 21
61.166 |BASEDEF ABSABSOLUTE 00000016 fs6 EQU 22
61.167 |BASEDEF ABSABSOLUTE 00000017 fs7 EQU 23
61.168 |BASEDEF ABSABSOLUTE 00000018 fs8 EQU 24
61.169 |BASEDEF ABSABSOLUTE 00000019 fs9 EQU 25
61.170 |BASEDEF ABSABSOLUTE 0000001A fs10 EQU 26
61.171 |BASEDEF ABSABSOLUTE 0000001B fs11 EQU 27
61.172 |BASEDEF ABSABSOLUTE 0000001C ft8 EQU 28
61.173 |BASEDEF ABSABSOLUTE 0000001D ft9 EQU 29
61.174 |BASEDEF ABSABSOLUTE 0000001E ft10 EQU 30
61.175 |BASEDEF ABSABSOLUTE 0000001F ft11 EQU 31
61.176 |BASEDEF //
61.177 |BASEDEF // Define Round Methods for Floating Point Arithmetic
61.178 |BASEDEF //
61.179 |BASEDEF ABSABSOLUTE 00000000 rm_rne EQU 0
61.180 |BASEDEF ABSABSOLUTE 00000001 rm_rtz EQU 1
61.181 |BASEDEF ABSABSOLUTE 00000002 rm_rdn EQU 2
61.182 |BASEDEF ABSABSOLUTE 00000003 rm_rup EQU 3
61.183 |BASEDEF ABSABSOLUTE 00000004 rm_rmm EQU 4
61.184 |BASEDEF ABSABSOLUTE 00000007 rm_dyn EQU 7
61.185 |BASEDEF //
61.186 |BASEDEF // Control registers
61.187 |BASEDEF //
61.188 |BASEDEF ABSABSOLUTE 00000001 fflags EQU 0x001
61.189 |BASEDEF ABSABSOLUTE 00000002 frm EQU 0x002
61.190 |BASEDEF ABSABSOLUTE 00000003 fcsr EQU 0x003
61.191 |BASEDEF ABSABSOLUTE 00000C00 cycle EQU 0xC00
61.192 |BASEDEF ABSABSOLUTE 00000C01 time EQU 0xC01
61.193 |BASEDEF ABSABSOLUTE 00000C02 instret EQU 0xC02
61.194 |BASEDEF ABSABSOLUTE 00000C80 cycleh EQU 0xC80
61.195 |BASEDEF ABSABSOLUTE 00000C81 timeh EQU 0xC81
61.196 |BASEDEF ABSABSOLUTE 00000C82 instreth EQU 0xC82
62 | //
[+][-] 63 | Code TextSect // Start .text section
Macro [TEXTSECT] source location is [JAR: /framework/macros/TextSect.mac]
63.1 |TEXTSECT 000000 Code SECTION ELF_SHT_PROGBITS,ELF_SHF_ALLOC+ELF_SHF_EXECINSTR,8,".text" // Text section definition
64 | C.SUSPEND // Do not use two byte opCode extension
Use of C extension has been suspended
65 | //
[+][-] 66 | dvasmavlinsert /> Entry label
Macro [ENTRY] source location is [JAR: /arch/RISCV/macros/Entry.mac]
67 | ENTRY Stack=!"" // Leaf entry, only A* and T* registers
67.1 |ENTRY EXPORT dvasmavlinsert
67.2 |ENTRY 000000 dvasmavlinsert DWRD 0[0]
ABSOLUTE, alignment [8], length [8], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 0000000000000000
Code [BIG ENDIAN] -> 0000000000000000
Code [DECIMAL ] -> 0
68 | // are used. No need to use a stack
69 | // or save/restore registers
[+][-] 70 | AVL.INSERT 0[a0], a1, InsCompString, duplKey, [t0-6,a2]
Macro [AVL.INSERT] source location is [JAR: /arch/RISCV/macros/Avl.insert.mac]
70.1 |AVL.INSERT 000000 83320500 LD t0, 0[a0] // Load root node addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00053283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 10
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 70.2 |AVL.INSERT IF ( t0 == 0 ), THEN // Check if tree is empty
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.2.1 |AVL.INSERT:IF __CondGen ( t0 == 0 ), true, Asm000004, Asm000002, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.2.1.1 ERT:IF:__CONDGEN|AVL.INSERT:IF:__CONDGEN 000004 639E0200 BNE t0, 0, Asm000002
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00029E63 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 0
Immediate PCRel........... 01C [HEX]
Immediate Sect. Offset.... 00000020 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1110 [BIN] bits [12:1]
70.2.1.2 ERT:IF:__CONDGEN|AVL.INSERT:IF:__CONDGEN 000008 Asm000004 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.2.2 |AVL.INSERT:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.3 |AVL.INSERT 000008 23B00500 SD 0, 0[a1] // Set left child to zero
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0005B023 [BIG ENDIAN]
Source 2 Register...... 0
Src. 1/Base Register...... 11
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 70.4 |AVL.INSERT AVL.__SETPA a1, t0, 0,, EVEN,, NOCLEAR, 8+0 // Set root node balance to zero
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.4.1 SERT:AVL.__SETPA|AVL.INSERT:AVL.__SETPA 00000C 93621000 ORI t0, 1[0] // Set balance bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00106293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 0
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
70.4.2 SERT:AVL.__SETPA|AVL.INSERT:AVL.__SETPA 000010 23B45500 SD t0, 8+0[a1] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0055B423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 11
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
70.5 |AVL.INSERT 000014 23B80500 SD 0, 16+0[a1] // Set right child to zero
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0005B823 [BIG ENDIAN]
Source 2 Register...... 0
Src. 1/Base Register...... 11
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
70.6 |AVL.INSERT 000018 2330B500 SD a1, 0[a0] // Set node as root
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00B53023 [BIG ENDIAN]
Source 2 Register...... 11
Src. 1/Base Register...... 10
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 70.7 |AVL.INSERT ELSE
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
70.7.1 |AVL.INSERT:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.7.2 |AVL.INSERT:ELSE 00001C 6F00402C JAL Asm000003
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 2C40006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +0002C4 [HEX]
Immediate Sect. Offset.... 000002E0 [HEX]
Immediate Encoded......... 0_00000000_0_0101100010 [BIN] Bits [20:1]
70.7.3 |AVL.INSERT:ELSE 000020 Asm000002 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.7.4 |AVL.INSERT:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 70.8 |AVL.INSERT DO // Start loop down
Macro [DO] source location is [JAR: /arch/RISCV/macros/Do.mac]
70.8.1 |AVL.INSERT:DO 000020 Asm000005 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.8.2 |AVL.INSERT:DO INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 70.9 |AVL.INSERT MV t1, t0 // copy next child to parent addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
70.9.1 |AVL.INSERT:MV 000020 13830200 ADDI t1, 0[t0]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00028313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 5
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 70.10 |AVL.INSERT InsCompString a1, t1, Asm000001, duplKey, [t2,t3,t4,t5,t6,a2] // Compare keys
Macro [INSCOMPSTRING] source location is [Inline macro from line 32 to line 54 included]
70.10.1 RT:INSCOMPSTRING|AVL.INSERT:INSCOMPSTRING 000024 83B38501 LD t2, 24[a1] // Load string addr from node 1
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0185B383 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 11
Immediate................. +018 [HEX]
Immediate Encoded......... 000000011000 [BIN] Bits [11:0]
70.10.2 RT:INSCOMPSTRING|AVL.INSERT:INSCOMPSTRING 000028 033E8301 LD t3, 24[t1] // Load string addr from node 2
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 01833E03 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 6
Immediate................. +018 [HEX]
Immediate Encoded......... 000000011000 [BIN] Bits [11:0]
[+][-] 70.10.3 RT:INSCOMPSTRING|AVL.INSERT:INSCOMPSTRING WHILE // Start DO block
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
70.10.3.1 COMPSTRING:WHILE|AVL.INSERT:INSCOMPSTRING:WHILE 00002C Asm000007 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.10.3.2 COMPSTRING:WHILE|AVL.INSERT:INSCOMPSTRING:WHILE 00002C Asm000008 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.10.3.3 COMPSTRING:WHILE|AVL.INSERT:INSCOMPSTRING:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.10.4 RT:INSCOMPSTRING|AVL.INSERT:INSCOMPSTRING 00002C 83CE0300 LBU t4, 0[t2] // Load first string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0003CE83 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 7
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
70.10.5 RT:INSCOMPSTRING|AVL.INSERT:INSCOMPSTRING 000030 034F0E00 LBU t5, 0[t3] // Load second string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 000E4F03 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 28
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 70.10.6 RT:INSCOMPSTRING|AVL.INSERT:INSCOMPSTRING IF (t4 > t5), GOTO, ID= Asm000001 // Done greater than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.10.6.1 INSCOMPSTRING:IF|AVL.INSERT:INSCOMPSTRING:IF __CondGen (t4 > t5), false, Asm000001, Asm000010, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 70.10.6.1.1 ING:IF:__CONDGEN|AVL.INSERT:INSCOMPSTRING:IF:__CONDGEN BGT t4, t5, Asm000001
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
70.10.6.1.1.70.10.6.1.1.1 IF:__CONDGEN:BGT|AVL.INSERT:INSCOMPSTRING:IF:__CONDGEN:BGT 000034 6346DF03 BLT t5, t4, Asm000001
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 03DF4663 [BIG ENDIAN]
Source 1 Register...... 30
Source 2 Register...... 29
Immediate PCRel........... 02C [HEX]
Immediate Sect. Offset.... 00000060 [HEX]
Immediate Bits [12:1]..... 0_0_000001_0110 [BIN] bits [12:1]
70.10.6.1.2 ING:IF:__CONDGEN|AVL.INSERT:INSCOMPSTRING:IF:__CONDGEN 000038 Asm000010 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 70.10.7 RT:INSCOMPSTRING|AVL.INSERT:INSCOMPSTRING IF (t4 < t5), BREAK // Done if less than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.10.7.1 INSCOMPSTRING:IF|AVL.INSERT:INSCOMPSTRING:IF __CondGen (t4 < t5), false, Asm000009, Asm000011, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.10.7.1.1 ING:IF:__CONDGEN|AVL.INSERT:INSCOMPSTRING:IF:__CONDGEN 000038 63CAEE01 BLT t4, t5, Asm000009
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 01EECA63 [BIG ENDIAN]
Source 1 Register...... 29
Source 2 Register...... 30
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 0000004C [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
70.10.7.1.2 ING:IF:__CONDGEN|AVL.INSERT:INSCOMPSTRING:IF:__CONDGEN 00003C Asm000011 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 70.10.8 RT:INSCOMPSTRING|AVL.INSERT:INSCOMPSTRING IF ( t5 == 0 ), GOTO, ID= duplKey // Equal condition with equal flag
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.10.8.1 INSCOMPSTRING:IF|AVL.INSERT:INSCOMPSTRING:IF __CondGen ( t5 == 0 ), false, duplKey, Asm000012, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.10.8.1.1 ING:IF:__CONDGEN|AVL.INSERT:INSCOMPSTRING:IF:__CONDGEN 00003C 63040F2A BEQ t5, 0, duplKey
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 2A0F0463 [BIG ENDIAN]
Source 1 Register...... 30
Source 2 Register...... 0
Immediate PCRel........... 2A8 [HEX]
Immediate Sect. Offset.... 000002E4 [HEX]
Immediate Bits [12:1]..... 0_0_010101_0100 [BIN] bits [12:1]
70.10.8.1.2 ING:IF:__CONDGEN|AVL.INSERT:INSCOMPSTRING:IF:__CONDGEN 000040 Asm000012 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.10.9 RT:INSCOMPSTRING|AVL.INSERT:INSCOMPSTRING 000040 93831300 ADDI t2, 1 // Get next char address (string 1)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00138393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 7
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
70.10.10 RT:INSCOMPSTRING|AVL.INSERT:INSCOMPSTRING 000044 130E1E00 ADDI t3, 1 // Get next char address (string 2)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 001E0E13 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 28
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 70.10.11 RT:INSCOMPSTRING|AVL.INSERT:INSCOMPSTRING ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
70.10.11.1 PSTRING:ENDWHILE|AVL.INSERT:INSCOMPSTRING:ENDWHILE 000048 6FF05FFE JAL Asm000008
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... FE5FF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -00001C [HEX]
Immediate Sect. Offset.... 0000002C [HEX]
Immediate Encoded......... 1_11111111_1_1111110010 [BIN] Bits [20:1]
70.10.11.2 PSTRING:ENDWHILE|AVL.INSERT:INSCOMPSTRING:ENDWHILE 00004C Asm000009 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.10.11.3 PSTRING:ENDWHILE|AVL.INSERT:INSCOMPSTRING:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.11 |AVL.INSERT 00004C 83320300 LD t0, 0[t1] // Load left child
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00033283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 6
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 70.12 |AVL.INSERT IF ( t0 != 0 ), CONTINUE // Child exists - continue
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.12.1 |AVL.INSERT:IF __CondGen ( t0 != 0 ), false, Asm000005, Asm000013, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.12.1.1 ERT:IF:__CONDGEN|AVL.INSERT:IF:__CONDGEN 000050 E39802FC BNE t0, 0, Asm000005
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... FC0298E3 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 0
Immediate PCRel........... -30 [HEX]
Immediate Sect. Offset.... 00000020 [HEX]
Immediate Bits [12:1]..... 1_1_111110_1000 [BIN] bits [12:1]
70.12.1.2 ERT:IF:__CONDGEN|AVL.INSERT:IF:__CONDGEN 000054 Asm000013 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.13 |AVL.INSERT 000054 2330B300 SD a1, 0[t1] // Insert new node as left child
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00B33023 [BIG ENDIAN]
Source 2 Register...... 11
Src. 1/Base Register...... 6
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 70.14 |AVL.INSERT AVL.__SETPA , t0, t1,, EVEN, LEFT, NOCLEAR, 8+0 // Set A Node as parent - left child
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.14.1 SERT:AVL.__SETPA|AVL.INSERT:AVL.__SETPA 000058 93625300 ORI t0, 5[t1] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00536293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 6
Immediate................. +005 [HEX]
Immediate Encoded......... 000000000101 [BIN] Bits [11:0]
[+][-] 70.15 |AVL.INSERT BREAK // Complete node initialization
Macro [BREAK] source location is [JAR: /arch/RISCV/macros/Break.mac]
70.15.1 AVL.INSERT:BREAK|AVL.INSERT:BREAK 00005C 6F004001 JAL Asm000006
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0140006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000014 [HEX]
Immediate Sect. Offset.... 00000070 [HEX]
Immediate Encoded......... 0_00000000_0_0000001010 [BIN] Bits [20:1]
70.16 |AVL.INSERT 000060 83320301 Asm000001 LD t0, 16+0[t1] // Get right child
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 01033283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 6
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
[+][-] 70.17 |AVL.INSERT IF ( t0 != 0 ), CONTINUE // Child exists - continue
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.17.1 |AVL.INSERT:IF __CondGen ( t0 != 0 ), false, Asm000005, Asm000014, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.17.1.1 ERT:IF:__CONDGEN|AVL.INSERT:IF:__CONDGEN 000064 E39E02FA BNE t0, 0, Asm000005
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... FA029EE3 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 0
Immediate PCRel........... -44 [HEX]
Immediate Sect. Offset.... 00000020 [HEX]
Immediate Bits [12:1]..... 1_1_111101_1110 [BIN] bits [12:1]
70.17.1.2 ERT:IF:__CONDGEN|AVL.INSERT:IF:__CONDGEN 000068 Asm000014 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.18 |AVL.INSERT 000068 2338B300 SD a1, 16+0[t1] // Insert node as right child
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00B33823 [BIG ENDIAN]
Source 2 Register...... 11
Src. 1/Base Register...... 6
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 70.19 |AVL.INSERT AVL.__SETPA , t0, t1,, EVEN, RIGHT, NOCLEAR, 8+0 // Set A Node as parent - right child
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.19.1 SERT:AVL.__SETPA|AVL.INSERT:AVL.__SETPA 00006C 93621300 ORI t0, 1[t1] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00136293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 6
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 70.20 |AVL.INSERT ENDDO
Macro [ENDDO] source location is [JAR: /arch/RISCV/macros/Enddo.mac]
70.20.1 AVL.INSERT:ENDDO|AVL.INSERT:ENDDO 000070 Asm000006 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.20.2 AVL.INSERT:ENDDO|AVL.INSERT:ENDDO INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.21 |AVL.INSERT
70.22 |AVL.INSERT 000070 23B00500 SD 0, 0[a1] //Set node left child to zero
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0005B023 [BIG ENDIAN]
Source 2 Register...... 0
Src. 1/Base Register...... 11
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
70.23 |AVL.INSERT 000074 23B45500 SD t0, 8+0[a1] // Set parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0055B423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 11
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
70.24 |AVL.INSERT 000078 23B80500 SD 0, 16+0[a1] // Set right child of node to zero
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0005B823 [BIG ENDIAN]
Source 2 Register...... 0
Src. 1/Base Register...... 11
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 70.25 |AVL.INSERT AVL.__BALNC INSERT, 0[a0], t0, 0, [t1,t2,t3,t4,t5,t6,a2] // Perform rotations if necessary
Macro [AVL.__BALNC] source location is [JAR: /arch/RISCV/macros/Avl.__balnc.mac]
70.25.1 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.2 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC // Balance the tree
70.25.3 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
[+][-] 70.25.4 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__EXTPA t2, t0 // Set up parent addr for WHILE loop
Macro [AVL.__EXTPA] source location is [JAR: /arch/RISCV/macros/Avl.__extpa.mac]
70.25.4.1 ALNC:AVL.__EXTPA|AVL.INSERT:AVL.__BALNC:AVL.__EXTPA 00007C 93F382FF ANDI t2, ~ 0b111[t0] // Extract parent node addr from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF82F393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 5
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
70.25.5 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
[+][-] 70.25.6 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC DO // Start balance loop
Macro [DO] source location is [JAR: /arch/RISCV/macros/Do.mac]
70.25.6.1 T:AVL.__BALNC:DO|AVL.INSERT:AVL.__BALNC:DO 000080 Asm000016 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.6.2 T:AVL.__BALNC:DO|AVL.INSERT:AVL.__BALNC:DO INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 70.25.7 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__EXTLT t4, t0 // Extract link type from parent
Macro [AVL.__EXTLT] source location is [JAR: /arch/RISCV/macros/Avl.__extlt.mac]
70.25.7.1 ALNC:AVL.__EXTLT|AVL.INSERT:AVL.__BALNC:AVL.__EXTLT 000080 93FE4200 ANDI t4, 0b100[t0] // Extract parent node link type
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0042FE93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 5
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
70.25.8 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000084 93DE1E00 SRLI t4, 1 // Convert link type
SRLI: Shift Logical Right Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001EDE93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 29
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
70.25.9 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000088 938EFEFF ADDI t4, -1 // ... to +/- 1 to be subtracted from balance
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFFE8E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 29
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
70.25.10 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 00008C 83B28300 LD t0, 8+0[t2] // Get parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0083B283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 7
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 70.25.11 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__EXTBL a2, t0 // Get balance of parent of deleted node
Macro [AVL.__EXTBL] source location is [JAR: /arch/RISCV/macros/Avl.__extbl.mac]
70.25.11.1 ALNC:AVL.__EXTBL|AVL.INSERT:AVL.__BALNC:AVL.__EXTBL 000090 13F63200 ANDI a2, 0b011[t0] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0032F613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 5
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.11.2 ALNC:AVL.__EXTBL|AVL.INSERT:AVL.__BALNC:AVL.__EXTBL 000094 1306F6FF ADDI a2, -1 // Subtract 1 to make it any of -1, 0, 1
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF60613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
70.25.12 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000098 3306D601 ADD a2, t4 // Add (insert) Subtract (remove) link for new balance
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 01D60633 [BIG ENDIAN]
Destination Register...... 12
Source 2 Register...... 29
Source 1 Register...... 12
70.25.13 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.13 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.14 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC // Check if left rotation
70.25.15 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
[+][-] 70.25.17 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC LI t4, 1 // Load compare constant
Macro [LI] source location is [JAR: /arch/RISCV/macros/Li.mac]
70.25.17.1 T:AVL.__BALNC:LI|AVL.INSERT:AVL.__BALNC:LI 00009C 930E1000 ADDI t4, 1[0] // Load immediate value
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00100E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 0
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 70.25.18 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( a2 > t4 ), THEN // Handle left substree too high
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.18.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( a2 > t4 ), true, Asm000020, Asm000018, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 70.25.18.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN BLE a2, t4, Asm000018
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
70.25.18.1.170.25.18.1.1.1 IF:__CONDGEN:BLE|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN:BLE 0000A0 63D8CE0E BGE t4, a2, Asm000018
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 0ECED863 [BIG ENDIAN]
Source 1 Register...... 29
Source 2 Register...... 12
Immediate PCRel........... 0F0 [HEX]
Immediate Sect. Offset.... 00000190 [HEX]
Immediate Bits [12:1]..... 0_0_000111_1000 [BIN] bits [12:1]
70.25.18.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0000A4 Asm000020 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.18.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.19 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0000A4 03B30300 LD t1, 0[t2] // Load B node addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0003B303 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 7
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
70.25.20 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0000A8 033E0301 LD t3, 16+0[t1] // Get C node addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 01033E03 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 6
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
70.25.21 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0000AC 03368300 LD a2, 8+0[t1] // get B node parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00833603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 6
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 70.25.22 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__EXTBL a2, a2 // Get B node balance
Macro [AVL.__EXTBL] source location is [JAR: /arch/RISCV/macros/Avl.__extbl.mac]
70.25.22.1 ALNC:AVL.__EXTBL|AVL.INSERT:AVL.__BALNC:AVL.__EXTBL 0000B0 13763600 ANDI a2, 0b011[a2] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.22.2 ALNC:AVL.__EXTBL|AVL.INSERT:AVL.__BALNC:AVL.__EXTBL 0000B4 1306F6FF ADDI a2, -1 // Subtract 1 to make it any of -1, 0, 1
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF60613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
70.25.23 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.23 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.24 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC // LL rotation - Top node is A, left child is B, right child of B node is C node if any
70.25.25 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
[+][-] 70.25.27 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( a2 >= 0 ), THEN // LL rotation if >= 0
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.27.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( a2 >= 0 ), true, Asm000023, Asm000021, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.27.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0000B8 63400604 BLT a2, 0, Asm000021
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 04064063 [BIG ENDIAN]
Source 1 Register...... 12
Source 2 Register...... 0
Immediate PCRel........... 040 [HEX]
Immediate Sect. Offset.... 000000F8 [HEX]
Immediate Bits [12:1]..... 0_0_000010_0000 [BIN] bits [12:1]
70.25.27.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0000BC Asm000023 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.27.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.28 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0000BC 23B0C301 SD t3, 0[t2] // Make C node right child of A node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01C3B023 [BIG ENDIAN]
Source 2 Register...... 28
Src. 1/Base Register...... 7
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 70.25.29 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( t3 != 0 ), THEN // Check if C node exists
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.29.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( t3 != 0 ), true, Asm000026, Asm000024, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.29.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0000C0 630C0E00 BEQ t3, 0, Asm000024
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 000E0C63 [BIG ENDIAN]
Source 1 Register...... 28
Source 2 Register...... 0
Immediate PCRel........... 018 [HEX]
Immediate Sect. Offset.... 000000D8 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1100 [BIN] bits [12:1]
70.25.29.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0000C4 Asm000026 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.29.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.30 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0000C4 833E8E00 LD t4, 8+0[t3] // Get parent field of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 008E3E83 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 28
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 70.25.31 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t3, t4, t4, t2,, LEFT, CLEAR, 8+0 // Set C node parent to A node - left link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.31.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0000C8 93FE3E00 ANDI t4, 3[t4] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 003EFE93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 29
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.31.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0000CC 93EE4E00 ORI t4, 4[t4] // Set link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 004EEE93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 29
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
70.25.31.3 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0000D0 B3EE7E00 OR t4, t2 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 007EEEB3 [BIG ENDIAN]
Destination Register...... 29
Source 2 Register...... 7
Source 1 Register...... 29
70.25.31.4 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0000D4 2334DE01 SD t4, 8+0[t3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01DE3423 [BIG ENDIAN]
Source 2 Register...... 29
Src. 1/Base Register...... 28
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.32 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.32.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 0000D8 Asm000024 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.32.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 0000D8 Asm000025 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.32.3 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 70.25.33 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t2, t4, t1,, EVEN, RIGHT, NOCLEAR, 8+0 // Set balance even - right link for A node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.33.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0000D8 936E1300 ORI t4, 1[t1] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00136E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 6
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
70.25.33.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0000DC 23B4D301 SD t4, 8+0[t2] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01D3B423 [BIG ENDIAN]
Source 2 Register...... 29
Src. 1/Base Register...... 7
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.34 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t1, t0, t0,, EVEN,, CLEAR, 8+0 // Set balance even - A node parent for B node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.34.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0000E0 93F2C2FF ANDI t0, -4[t0] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC2F293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
70.25.34.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0000E4 93E21200 ORI t0, 1[t0] // Set balance bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0012E293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
70.25.34.3 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0000E8 23345300 SD t0, 8+0[t1] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00533423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 6
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
70.25.35 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0000EC 23387300 SD t2, 16+0[t1] // Set A node as right child of B node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00733823 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 6
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 70.25.36 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC MV t2, t1 // Copy B node addr for rotation completion code
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
70.25.36.1 T:AVL.__BALNC:MV|AVL.INSERT:AVL.__BALNC:MV 0000F0 93030300 ADDI t2, 0[t1]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00030393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 6
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 70.25.37 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC GOTO Asm000015 // Execute rotation completion code
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
70.25.37.1 AVL.__BALNC:GOTO|AVL.INSERT:AVL.__BALNC:GOTO 0000F4 6F00C01B JAL 0, Asm000015 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 1BC0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +0001BC [HEX]
Immediate Sect. Offset.... 000002B0 [HEX]
Immediate Encoded......... 0_00000000_0_0011011110 [BIN] Bits [20:1]
[+][-] 70.25.38 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.38.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 0000F8 Asm000021 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.38.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 0000F8 Asm000022 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.38.3 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.39 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.39 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.40 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC // LR Rotation - Top node is A, left child is B, its right child is C
70.25.41 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.43 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0000F8 833E8E00 LD t4, 8+0[t3] // Get parent field from C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 008E3E83 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 28
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
70.25.44 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
[+][-] 70.25.45 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__EXTBL t4, t4 // Get balance of C node
Macro [AVL.__EXTBL] source location is [JAR: /arch/RISCV/macros/Avl.__extbl.mac]
70.25.45.1 ALNC:AVL.__EXTBL|AVL.INSERT:AVL.__BALNC:AVL.__EXTBL 0000FC 93FE3E00 ANDI t4, 0b011[t4] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 003EFE93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 29
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.45.2 ALNC:AVL.__EXTBL|AVL.INSERT:AVL.__BALNC:AVL.__EXTBL 000100 938EFEFF ADDI t4, -1 // Subtract 1 to make it any of -1, 0, 1
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFFE8E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 29
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
70.25.46 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
[+][-] 70.25.47 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( t4 == 0 ), THEN // Check if C node balance is even
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.47.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( t4 == 0 ), true, Asm000029, Asm000027, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.47.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 000104 63980E00 BNE t4, 0, Asm000027
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 000E9863 [BIG ENDIAN]
Source 1 Register...... 29
Source 2 Register...... 0
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 00000114 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
70.25.47.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 000108 Asm000029 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.47.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 70.25.48 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t5, t3,, EVEN, LEFT, NOCLEAR, 8+0 // Set B node parent even/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.48.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000108 136F5E00 ORI t5, 5[t3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 005E6F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 28
Immediate................. +005 [HEX]
Immediate Encoded......... 000000000101 [BIN] Bits [11:0]
[+][-] 70.25.49 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t6, t3,, EVEN, RIGHT, NOCLEAR, 8+0 // Set A node parent even/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.49.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 00010C 936F1E00 ORI t6, 1[t3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 001E6F93 [BIG ENDIAN]
Destination Register...... 31
Source 1 Register...... 28
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 70.25.50 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ELSEIF ( t4 > 0 ) // Check if C node balance is high on left
Macro [ELSEIF] source location is [JAR: /arch/RISCV/macros/ElseIf.mac]
70.25.50.1 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.50.2 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF 000110 6F00C001 JAL Asm000028
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 01C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00001C [HEX]
Immediate Sect. Offset.... 0000012C [HEX]
Immediate Encoded......... 0_00000000_0_0000001110 [BIN] Bits [20:1]
70.25.50.3 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF 000114 Asm000027 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 70.25.50.4 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF __CondGen ( t4 > 0 ), true, Asm000031, Asm000030, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 70.25.50.4.1 ELSEIF:__CONDGEN|AVL.INSERT:AVL.__BALNC:ELSEIF:__CONDGEN BLE t4, 0, Asm000030
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
70.25.50.4.170.25.50.4.1.1 IF:__CONDGEN:BLE|AVL.INSERT:AVL.__BALNC:ELSEIF:__CONDGEN:BLE 000114 6358D001 BGE 0, t4, Asm000030
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 01D05863 [BIG ENDIAN]
Source 1 Register...... 0
Source 2 Register...... 29
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 00000124 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
70.25.50.4.2 ELSEIF:__CONDGEN|AVL.INSERT:AVL.__BALNC:ELSEIF:__CONDGEN 000118 Asm000031 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.50.5 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 70.25.51 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t5, t3,, EVEN, LEFT, NOCLEAR, 8+0 // Set B node parent even/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.51.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000118 136F5E00 ORI t5, 5[t3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 005E6F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 28
Immediate................. +005 [HEX]
Immediate Encoded......... 000000000101 [BIN] Bits [11:0]
[+][-] 70.25.52 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t6, t3,, MINUS, RIGHT, NOCLEAR, 8+0 // Set A node parent minus/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
[+][-] 70.25.52.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA MV t6, t3 // Copy parent field - Set balance and link bits
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
70.25.52.1.1 C:AVL.__SETPA:MV|AVL.INSERT:AVL.__BALNC:AVL.__SETPA:MV 00011C 930F0E00 ADDI t6, 0[t3]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 000E0F93 [BIG ENDIAN]
Destination Register...... 31
Source 1 Register...... 28
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 70.25.53 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ELSE // Balance is high on right
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
70.25.53.1 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.53.2 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE 000120 6F00C000 JAL Asm000028
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 00C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00000C [HEX]
Immediate Sect. Offset.... 0000012C [HEX]
Immediate Encoded......... 0_00000000_0_0000000110 [BIN] Bits [20:1]
70.25.53.3 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE 000124 Asm000030 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.53.4 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 70.25.54 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t5, t3,, PLUS, LEFT, NOCLEAR, 8+0 // Set B node parent plus/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.54.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000124 136F6E00 ORI t5, 6[t3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 006E6F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 28
Immediate................. +006 [HEX]
Immediate Encoded......... 000000000110 [BIN] Bits [11:0]
[+][-] 70.25.55 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t6, t3,, EVEN, RIGHT, NOCLEAR, 8+0 // Set A node parent even/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.55.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000128 936F1E00 ORI t6, 1[t3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 001E6F93 [BIG ENDIAN]
Destination Register...... 31
Source 1 Register...... 28
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 70.25.56 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.56.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 00012C Asm000028 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.56.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.57 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.58 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 00012C 2334E301 SD t5, 8+0[t1] // Store B node parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01E33423 [BIG ENDIAN]
Source 2 Register...... 30
Src. 1/Base Register...... 6
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
70.25.59 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000130 23B4F301 SD t6, 8+0[t2] // Store A node parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01F3B423 [BIG ENDIAN]
Source 2 Register...... 31
Src. 1/Base Register...... 7
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
70.25.60 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.61 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000134 833E0E00 LD t4, 0[t3] // Get left child of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 000E3E83 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 28
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
70.25.62 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000138 2338D301 SD t4, 16+0[t1] // Store it as right child of B node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01D33823 [BIG ENDIAN]
Source 2 Register...... 29
Src. 1/Base Register...... 6
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 70.25.63 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( t4 != 0 ), THEN // Check if C node left child exists
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.63.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( t4 != 0 ), true, Asm000034, Asm000032, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.63.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 00013C 638A0E00 BEQ t4, 0, Asm000032
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 000E8A63 [BIG ENDIAN]
Source 1 Register...... 29
Source 2 Register...... 0
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 00000150 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
70.25.63.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 000140 Asm000034 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.63.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.64 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000140 03BF8E00 LD t5, 8+0[t4] // Get C node left child parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 008EBF03 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 29
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 70.25.65 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t4, t5, t5, t1,, RIGHT, CLEAR, 8+0 // Set C node child parent to B node - right link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.65.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000144 137F3F00 ANDI t5, 3[t5] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 003F7F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.65.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000148 336F6F00 OR t5, t1 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 006F6F33 [BIG ENDIAN]
Destination Register...... 30
Source 2 Register...... 6
Source 1 Register...... 30
70.25.65.3 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 00014C 23B4EE01 SD t5, 8+0[t4] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01EEB423 [BIG ENDIAN]
Source 2 Register...... 30
Src. 1/Base Register...... 29
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.66 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.66.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 000150 Asm000032 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.66.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 000150 Asm000033 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.66.3 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.67 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.68 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000150 833E0E01 LD t4, 16+0[t3] // get right child of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 010E3E83 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 28
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
70.25.69 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000154 23B0D301 SD t4, 0[t2] // Store it as left child of A node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01D3B023 [BIG ENDIAN]
Source 2 Register...... 29
Src. 1/Base Register...... 7
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 70.25.70 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( t4 != 0 ), THEN // Check if node exists
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.70.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( t4 != 0 ), true, Asm000037, Asm000035, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.70.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 000158 638C0E00 BEQ t4, 0, Asm000035
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 000E8C63 [BIG ENDIAN]
Source 1 Register...... 29
Source 2 Register...... 0
Immediate PCRel........... 018 [HEX]
Immediate Sect. Offset.... 00000170 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1100 [BIN] bits [12:1]
70.25.70.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 00015C Asm000037 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.70.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.71 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 00015C 03BF8E00 LD t5, 8+0[t4] // Get C node right child parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 008EBF03 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 29
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 70.25.72 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t4, t5, t5, t2,, LEFT, CLEAR, 8+0 // Set C node child parent to B node - right link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.72.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000160 137F3F00 ANDI t5, 3[t5] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 003F7F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.72.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000164 136F4F00 ORI t5, 4[t5] // Set link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 004F6F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
70.25.72.3 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000168 336F7F00 OR t5, t2 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 007F6F33 [BIG ENDIAN]
Destination Register...... 30
Source 2 Register...... 7
Source 1 Register...... 30
70.25.72.4 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 00016C 23B4EE01 SD t5, 8+0[t4] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01EEB423 [BIG ENDIAN]
Source 2 Register...... 30
Src. 1/Base Register...... 29
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.73 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.73.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 000170 Asm000035 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.73.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 000170 Asm000036 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.73.3 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.74 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000170 23306E00 SD t1, 0[t3] // Set B node as left child of C node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 006E3023 [BIG ENDIAN]
Source 2 Register...... 6
Src. 1/Base Register...... 28
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
70.25.75 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000174 23387E00 SD t2, 16+0[t3] // Set A node as right child of C node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 007E3823 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 28
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
70.25.76 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
[+][-] 70.25.77 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t3, t0, t0,, EVEN,, CLEAR, 8+0 // Store A node parent in C node parnent field - even balance
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.77.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000178 93F2C2FF ANDI t0, -4[t0] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC2F293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
70.25.77.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 00017C 93E21200 ORI t0, 1[t0] // Set balance bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0012E293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
70.25.77.3 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000180 23345E00 SD t0, 8+0[t3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 005E3423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 28
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.78 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC MV t2, t3 // Copy C node addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
70.25.78.1 T:AVL.__BALNC:MV|AVL.INSERT:AVL.__BALNC:MV 000184 93030E00 ADDI t2, 0[t3]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 000E0393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 28
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 70.25.79 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC GOTO Asm000015 // Execute rotation completion code
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
70.25.79.1 AVL.__BALNC:GOTO|AVL.INSERT:AVL.__BALNC:GOTO 000188 6F008012 JAL 0, Asm000015 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 1280006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000128 [HEX]
Immediate Sect. Offset.... 000002B0 [HEX]
Immediate Encoded......... 0_00000000_0_0010010100 [BIN] Bits [20:1]
70.25.80 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.80 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.81 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC // Check if right rotation
70.25.82 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
[+][-] 70.25.84 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ELSEIF ( a2 < t4 ), Precode= [!"LI t4, -1"]
Macro [ELSEIF] source location is [JAR: /arch/RISCV/macros/ElseIf.mac]
70.25.84.1 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.84.2 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF 00018C 6F00000F JAL Asm000019
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0F00006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +0000F0 [HEX]
Immediate Sect. Offset.... 0000027C [HEX]
Immediate Encoded......... 0_00000000_0_0001111000 [BIN] Bits [20:1]
70.25.84.3 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF 000190 Asm000018 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 70.25.84.4 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF LI t4, -1
Macro [LI] source location is [JAR: /arch/RISCV/macros/Li.mac]
70.25.84.4.1 _BALNC:ELSEIF:LI|AVL.INSERT:AVL.__BALNC:ELSEIF:LI 000190 930EF0FF ADDI t4, -1[0] // Load immediate value
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF00E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 0
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
[+][-] 70.25.84.5 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF __CondGen ( a2 < t4 ), true, Asm000039, Asm000038, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.84.5.1 ELSEIF:__CONDGEN|AVL.INSERT:AVL.__BALNC:ELSEIF:__CONDGEN 000194 6354D60F BGE a2, t4, Asm000038
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 0FD65463 [BIG ENDIAN]
Source 1 Register...... 12
Source 2 Register...... 29
Immediate PCRel........... 0E8 [HEX]
Immediate Sect. Offset.... 0000027C [HEX]
Immediate Bits [12:1]..... 0_0_000111_0100 [BIN] bits [12:1]
70.25.84.5.2 ELSEIF:__CONDGEN|AVL.INSERT:AVL.__BALNC:ELSEIF:__CONDGEN 000198 Asm000039 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.84.6 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.84 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC // Handle right substree too high
70.25.86 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000198 03B30301 LD t1, 16+0[t2] // Load B node addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0103B303 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 7
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
70.25.87 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 00019C 033E0300 LD t3, 0[t1] // Get C node addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00033E03 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 6
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
70.25.88 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0001A0 03368300 LD a2, 8+0[t1] // get B node parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00833603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 6
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 70.25.89 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__EXTBL a2, a2 // Get B node balance
Macro [AVL.__EXTBL] source location is [JAR: /arch/RISCV/macros/Avl.__extbl.mac]
70.25.89.1 ALNC:AVL.__EXTBL|AVL.INSERT:AVL.__BALNC:AVL.__EXTBL 0001A4 13763600 ANDI a2, 0b011[a2] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.89.2 ALNC:AVL.__EXTBL|AVL.INSERT:AVL.__BALNC:AVL.__EXTBL 0001A8 1306F6FF ADDI a2, -1 // Subtract 1 to make it any of -1, 0, 1
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF60613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
70.25.90 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.90 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.91 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC // RR Rotation - Top node is A, left child is B, its right child is C if it exists
70.25.92 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
[+][-] 70.25.94 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( a2 <= 0 ), THEN // Check if RR rotation
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.94.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( a2 <= 0 ), true, Asm000042, Asm000040, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 70.25.94.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN BGT a2, 0, Asm000040
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
70.25.94.1.170.25.94.1.1.1 IF:__CONDGEN:BGT|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN:BGT 0001AC 634EC002 BLT 0, a2, Asm000040
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 02C04E63 [BIG ENDIAN]
Source 1 Register...... 0
Source 2 Register...... 12
Immediate PCRel........... 03C [HEX]
Immediate Sect. Offset.... 000001E8 [HEX]
Immediate Bits [12:1]..... 0_0_000001_1110 [BIN] bits [12:1]
70.25.94.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0001B0 Asm000042 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.94.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.95 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0001B0 23B8C301 SD t3, 16+0[t2] // Make B node left child new right child A node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01C3B823 [BIG ENDIAN]
Source 2 Register...... 28
Src. 1/Base Register...... 7
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 70.25.96 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( t3 != 0 ), THEN
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.96.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( t3 != 0 ), true, Asm000045, Asm000043, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.96.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0001B4 630A0E00 BEQ t3, 0, Asm000043
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 000E0A63 [BIG ENDIAN]
Source 1 Register...... 28
Source 2 Register...... 0
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 000001C8 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
70.25.96.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0001B8 Asm000045 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.96.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.97 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0001B8 833E8E00 LD t4, 8+0[t3] // Get parent field of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 008E3E83 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 28
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 70.25.98 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t3, t4, t4, t2,, RIGHT, CLEAR, 8+0 // Set C node parent to A node - right link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.98.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0001BC 93FE3E00 ANDI t4, 3[t4] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 003EFE93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 29
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.98.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0001C0 B3EE7E00 OR t4, t2 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 007EEEB3 [BIG ENDIAN]
Destination Register...... 29
Source 2 Register...... 7
Source 1 Register...... 29
70.25.98.3 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0001C4 2334DE01 SD t4, 8+0[t3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01DE3423 [BIG ENDIAN]
Source 2 Register...... 29
Src. 1/Base Register...... 28
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.99 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.99.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 0001C8 Asm000043 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.99.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 0001C8 Asm000044 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.99.3 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 70.25.100 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t2, t4, t1,, EVEN, LEFT, NOCLEAR, 8+0 // Set balance even - right link for A node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.100.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0001C8 936E5300 ORI t4, 5[t1] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00536E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 6
Immediate................. +005 [HEX]
Immediate Encoded......... 000000000101 [BIN] Bits [11:0]
70.25.100.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0001CC 23B4D301 SD t4, 8+0[t2] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01D3B423 [BIG ENDIAN]
Source 2 Register...... 29
Src. 1/Base Register...... 7
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.101 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t1, t0, t0,, EVEN,, CLEAR, 8+0 // Set balance even - A node parent for B node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.101.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0001D0 93F2C2FF ANDI t0, -4[t0] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC2F293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
70.25.101.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0001D4 93E21200 ORI t0, 1[t0] // Set balance bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0012E293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
70.25.101.3 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0001D8 23345300 SD t0, 8+0[t1] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00533423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 6
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
70.25.102 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0001DC 23307300 SD t2, 0[t1] // Set left child of B node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00733023 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 6
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
70.25.103 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
[+][-] 70.25.104 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC MV t2, t1 // Copy B node addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
70.25.104.1 T:AVL.__BALNC:MV|AVL.INSERT:AVL.__BALNC:MV 0001E0 93030300 ADDI t2, 0[t1]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00030393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 6
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 70.25.105 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC GOTO Asm000015 // Execute rotation completion code
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
70.25.105.1 AVL.__BALNC:GOTO|AVL.INSERT:AVL.__BALNC:GOTO 0001E4 6F00C00C JAL 0, Asm000015 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0CC0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +0000CC [HEX]
Immediate Sect. Offset.... 000002B0 [HEX]
Immediate Encoded......... 0_00000000_0_0001100110 [BIN] Bits [20:1]
[+][-] 70.25.106 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.106.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 0001E8 Asm000040 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.106.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 0001E8 Asm000041 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.106.3 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.107 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.107 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.108 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC // RL Rotation - Top node is A, right child is B, its left child is C
70.25.109 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.111 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0001E8 833E8E00 LD t4, 8+0[t3] // Get parent field from C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 008E3E83 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 28
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 70.25.112 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__EXTBL t4, t4 // Get balance of C node
Macro [AVL.__EXTBL] source location is [JAR: /arch/RISCV/macros/Avl.__extbl.mac]
70.25.112.1 ALNC:AVL.__EXTBL|AVL.INSERT:AVL.__BALNC:AVL.__EXTBL 0001EC 93FE3E00 ANDI t4, 0b011[t4] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 003EFE93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 29
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.112.2 ALNC:AVL.__EXTBL|AVL.INSERT:AVL.__BALNC:AVL.__EXTBL 0001F0 938EFEFF ADDI t4, -1 // Subtract 1 to make it any of -1, 0, 1
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFFE8E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 29
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
70.25.113 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
[+][-] 70.25.114 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( t4 == 0 ), THEN // Check if C node balance is even
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.114.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( t4 == 0 ), true, Asm000048, Asm000046, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.114.1.70.25.114.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0001F4 63980E00 BNE t4, 0, Asm000046
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 000E9863 [BIG ENDIAN]
Source 1 Register...... 29
Source 2 Register...... 0
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 00000204 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
70.25.114.1.70.25.114.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0001F8 Asm000048 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.114.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 70.25.115 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t5, t3,, EVEN, RIGHT, NOCLEAR, 8+0 // Set B node parent even/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.115.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0001F8 136F1E00 ORI t5, 1[t3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 001E6F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 28
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 70.25.116 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t6, t3,, EVEN, LEFT, NOCLEAR, 8+0 // Set A node parent even/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.116.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 0001FC 936F5E00 ORI t6, 5[t3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 005E6F93 [BIG ENDIAN]
Destination Register...... 31
Source 1 Register...... 28
Immediate................. +005 [HEX]
Immediate Encoded......... 000000000101 [BIN] Bits [11:0]
[+][-] 70.25.117 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ELSEIF ( t4 < 0 ) // Check if C node balance is high on right
Macro [ELSEIF] source location is [JAR: /arch/RISCV/macros/ElseIf.mac]
70.25.117.1 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.117.2 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF 000200 6F00C001 JAL Asm000047
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 01C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00001C [HEX]
Immediate Sect. Offset.... 0000021C [HEX]
Immediate Encoded......... 0_00000000_0_0000001110 [BIN] Bits [20:1]
70.25.117.3 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF 000204 Asm000046 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 70.25.117.4 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF __CondGen ( t4 < 0 ), true, Asm000050, Asm000049, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.117.4.70.25.117.4.1 ELSEIF:__CONDGEN|AVL.INSERT:AVL.__BALNC:ELSEIF:__CONDGEN 000204 63D80E00 BGE t4, 0, Asm000049
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 000ED863 [BIG ENDIAN]
Source 1 Register...... 29
Source 2 Register...... 0
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 00000214 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
70.25.117.4.70.25.117.4.2 ELSEIF:__CONDGEN|AVL.INSERT:AVL.__BALNC:ELSEIF:__CONDGEN 000208 Asm000050 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.117.5 L.__BALNC:ELSEIF|AVL.INSERT:AVL.__BALNC:ELSEIF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 70.25.118 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t5, t3,, EVEN, RIGHT, NOCLEAR, 8+0 // Set B node parent even/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.118.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000208 136F1E00 ORI t5, 1[t3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 001E6F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 28
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 70.25.119 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t6, t3,, PLUS, LEFT, NOCLEAR, 8+0 // Set A node parent plus/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.119.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 00020C 936F6E00 ORI t6, 6[t3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 006E6F93 [BIG ENDIAN]
Destination Register...... 31
Source 1 Register...... 28
Immediate................. +006 [HEX]
Immediate Encoded......... 000000000110 [BIN] Bits [11:0]
[+][-] 70.25.120 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ELSE // Balance is high on left
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
70.25.120.1 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.120.2 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE 000210 6F00C000 JAL Asm000047
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 00C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00000C [HEX]
Immediate Sect. Offset.... 0000021C [HEX]
Immediate Encoded......... 0_00000000_0_0000000110 [BIN] Bits [20:1]
70.25.120.3 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE 000214 Asm000049 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.120.4 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 70.25.121 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t5, t3,, MINUS, RIGHT, NOCLEAR, 8+0 // Set B node parent minus/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
[+][-] 70.25.121.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA MV t5, t3 // Copy parent field - Set balance and link bits
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
70.25.121.1.70.25.121.1.1 C:AVL.__SETPA:MV|AVL.INSERT:AVL.__BALNC:AVL.__SETPA:MV 000214 130F0E00 ADDI t5, 0[t3]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 000E0F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 28
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 70.25.122 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA , t6, t3,, EVEN, LEFT, NOCLEAR, 8+0 // Set A node parent even/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.122.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000218 936F5E00 ORI t6, 5[t3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 005E6F93 [BIG ENDIAN]
Destination Register...... 31
Source 1 Register...... 28
Immediate................. +005 [HEX]
Immediate Encoded......... 000000000101 [BIN] Bits [11:0]
[+][-] 70.25.123 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.123.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 00021C Asm000047 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.123.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.124 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 00021C 2334E301 SD t5, 8+0[t1] // Store B node parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01E33423 [BIG ENDIAN]
Source 2 Register...... 30
Src. 1/Base Register...... 6
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
70.25.125 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000220 23B4F301 SD t6, 8+0[t2] // Store A node parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01F3B423 [BIG ENDIAN]
Source 2 Register...... 31
Src. 1/Base Register...... 7
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
70.25.126 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.127 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000224 833E0E01 LD t4, 16+0[t3] // Get right child of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 010E3E83 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 28
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
70.25.128 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000228 2330D301 SD t4, 0[t1] // Store it as left child of B node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01D33023 [BIG ENDIAN]
Source 2 Register...... 29
Src. 1/Base Register...... 6
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 70.25.129 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( t4 != 0 ), THEN // Check if node exists
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.129.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( t4 != 0 ), true, Asm000053, Asm000051, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.129.1.70.25.129.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 00022C 638C0E00 BEQ t4, 0, Asm000051
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 000E8C63 [BIG ENDIAN]
Source 1 Register...... 29
Source 2 Register...... 0
Immediate PCRel........... 018 [HEX]
Immediate Sect. Offset.... 00000244 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1100 [BIN] bits [12:1]
70.25.129.1.70.25.129.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 000230 Asm000053 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.129.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.130 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000230 03BF8E00 LD t5, 8+0[t4] // Get its parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 008EBF03 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 29
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 70.25.131 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t4, t5, t5, t1,, LEFT, CLEAR, 8+0 // Set C node child parent to B node - left link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.131.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000234 137F3F00 ANDI t5, 3[t5] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 003F7F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.131.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000238 136F4F00 ORI t5, 4[t5] // Set link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 004F6F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
70.25.131.3 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 00023C 336F6F00 OR t5, t1 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 006F6F33 [BIG ENDIAN]
Destination Register...... 30
Source 2 Register...... 6
Source 1 Register...... 30
70.25.131.4 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000240 23B4EE01 SD t5, 8+0[t4] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01EEB423 [BIG ENDIAN]
Source 2 Register...... 30
Src. 1/Base Register...... 29
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.132 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.132.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 000244 Asm000051 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.132.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 000244 Asm000052 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.132.3 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.133 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.134 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000244 833E0E00 LD t4, 0[t3] // Get left child of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 000E3E83 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 28
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
70.25.135 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000248 23B8D301 SD t4, 16+0[t2] // Store it as right child of A node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01D3B823 [BIG ENDIAN]
Source 2 Register...... 29
Src. 1/Base Register...... 7
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 70.25.136 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( t4 != 0 ), THEN // Check if node exists
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.136.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( t4 != 0 ), true, Asm000056, Asm000054, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.136.1.70.25.136.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 00024C 638A0E00 BEQ t4, 0, Asm000054
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 000E8A63 [BIG ENDIAN]
Source 1 Register...... 29
Source 2 Register...... 0
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 00000260 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
70.25.136.1.70.25.136.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 000250 Asm000056 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.136.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.137 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000250 03BF8E00 LD t5, 8+0[t4] // Get its parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 008EBF03 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 29
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 70.25.138 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t4, t5, t5, t2,, RIGHT, CLEAR, 8+0 // Set C node child parent to B node - right link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.138.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000254 137F3F00 ANDI t5, 3[t5] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 003F7F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.138.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000258 336F7F00 OR t5, t2 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 007F6F33 [BIG ENDIAN]
Destination Register...... 30
Source 2 Register...... 7
Source 1 Register...... 30
70.25.138.3 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 00025C 23B4EE01 SD t5, 8+0[t4] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01EEB423 [BIG ENDIAN]
Source 2 Register...... 30
Src. 1/Base Register...... 29
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.139 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.139.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 000260 Asm000054 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.139.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 000260 Asm000055 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.139.3 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.140 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000260 23386E00 SD t1, 16+0[t3] // Set B node as right child of C node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 006E3823 [BIG ENDIAN]
Source 2 Register...... 6
Src. 1/Base Register...... 28
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
70.25.141 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000264 23307E00 SD t2, 0[t3] // Set A node as left child of C node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 007E3023 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 28
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
70.25.142 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
[+][-] 70.25.143 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__SETPA t3, t0, t0,, EVEN,, CLEAR, 8+0 // Store A node parent in C node parnent field - even balance
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
70.25.143.1 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000268 93F2C2FF ANDI t0, -4[t0] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC2F293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
70.25.143.2 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 00026C 93E21200 ORI t0, 1[t0] // Set balance bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0012E293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
70.25.143.3 ALNC:AVL.__SETPA|AVL.INSERT:AVL.__BALNC:AVL.__SETPA 000270 23345E00 SD t0, 8+0[t3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 005E3423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 28
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.144 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC MV t2, t3 // Copy C node addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
70.25.144.1 T:AVL.__BALNC:MV|AVL.INSERT:AVL.__BALNC:MV 000274 93030E00 ADDI t2, 0[t3]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 000E0393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 28
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 70.25.145 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC GOTO Asm000015 // Execute rotation completion code
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
70.25.145.1 AVL.__BALNC:GOTO|AVL.INSERT:AVL.__BALNC:GOTO 000278 6F008003 JAL 0, Asm000015 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0380006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000038 [HEX]
Immediate Sect. Offset.... 000002B0 [HEX]
Immediate Encoded......... 0_00000000_0_0000011100 [BIN] Bits [20:1]
[+][-] 70.25.146 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.146.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 00027C Asm000038 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.146.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 00027C Asm000019 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.146.3 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.147 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.148 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.149 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC // No rotation
70.25.150 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.151 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 00027C 130F1600 ADDI t5, 1[a2] // Encode balance
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00160F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 12
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
70.25.152 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000280 137F3F00 ANDI t5, 0b011 // Keep low bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 003F7F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
[+][-] 70.25.153 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__EXTPA t4, t0 // Extract addr of next node up
Macro [AVL.__EXTPA] source location is [JAR: /arch/RISCV/macros/Avl.__extpa.mac]
70.25.153.1 ALNC:AVL.__EXTPA|AVL.INSERT:AVL.__BALNC:AVL.__EXTPA 000284 93FE82FF ANDI t4, ~ 0b111[t0] // Extract parent node addr from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF82FE93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 5
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
70.25.154 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
[+][-] 70.25.155 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( t4 == 0 ), THEN // Check if root node
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.155.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( t4 == 0 ), true, Asm000059, Asm000057, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.155.1.70.25.155.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 000288 63980E00 BNE t4, 0, Asm000057
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 000E9863 [BIG ENDIAN]
Source 1 Register...... 29
Source 2 Register...... 0
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 00000298 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
70.25.155.1.70.25.155.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 00028C Asm000059 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.155.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.156 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 00028C 23307500 SD t2, 0[a0] // Update header
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00753023 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 10
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
70.25.157 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000290 23B4E301 SD t5, 8+0[t2] // Store balance only in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01E3B423 [BIG ENDIAN]
Source 2 Register...... 30
Src. 1/Base Register...... 7
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.158 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC BREAK // Done
Macro [BREAK] source location is [JAR: /arch/RISCV/macros/Break.mac]
70.25.158.1 VL.__BALNC:BREAK|AVL.INSERT:AVL.__BALNC:BREAK 000294 6F00C004 JAL Asm000017
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 04C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00004C [HEX]
Immediate Sect. Offset.... 000002E0 [HEX]
Immediate Encoded......... 0_00000000_0_0000100110 [BIN] Bits [20:1]
[+][-] 70.25.159 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.159.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 000298 Asm000057 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.159.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 000298 Asm000058 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.159.3 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.160 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.161 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 000298 93F2C2FF ANDI t0, ~ 0b011 // Clear balance bits in parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC2F293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
70.25.162 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 00029C B3E2E201 OR t0, t5 // Insert new balance
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 01E2E2B3 [BIG ENDIAN]
Destination Register...... 5
Source 2 Register...... 30
Source 1 Register...... 5
70.25.163 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0002A0 23B45300 SD t0,8+0[t2] // Store parent field in node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0053B423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 7
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.164 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC MV t2, t4 // Copy next node up addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
70.25.164.1 T:AVL.__BALNC:MV|AVL.INSERT:AVL.__BALNC:MV 0002A4 93830E00 ADDI t2, 0[t4]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 000E8393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 29
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 70.25.165 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF (a2 != 0), CONTINUE // Continue since balance is not zero
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.165.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen (a2 != 0), false, Asm000016, Asm000060, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.165.1.70.25.165.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0002A8 E31C06DC BNE a2, 0, Asm000016
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... DC061CE3 [BIG ENDIAN]
Source 1 Register...... 12
Source 2 Register...... 0
Immediate PCRel........... -228 [HEX]
Immediate Sect. Offset.... 00000080 [HEX]
Immediate Bits [12:1]..... 1_1_101110_1100 [BIN] bits [12:1]
70.25.165.1.70.25.165.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0002AC Asm000060 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 70.25.166 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC BREAK // Done otherwise
Macro [BREAK] source location is [JAR: /arch/RISCV/macros/Break.mac]
70.25.166.1 VL.__BALNC:BREAK|AVL.INSERT:AVL.__BALNC:BREAK 0002AC 6F004003 JAL Asm000017
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0340006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000034 [HEX]
Immediate Sect. Offset.... 000002E0 [HEX]
Immediate Encoded......... 0_00000000_0_0000011010 [BIN] Bits [20:1]
70.25.167 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.167 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
70.25.168 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC // Rotation completion common code
70.25.169 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC //
[+][-] 70.25.171 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC Asm000015 AVL.__EXTPA t5, t0 // Get A node parent addr
Macro [AVL.__EXTPA] source location is [JAR: /arch/RISCV/macros/Avl.__extpa.mac]
70.25.171.1 ALNC:AVL.__EXTPA|AVL.INSERT:AVL.__BALNC:AVL.__EXTPA 0002B0 13FF82FF Asm000015 ANDI t5, ~ 0b111[t0] // Extract parent node addr from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF82FF13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 5
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 70.25.172 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( t5 == 0 ), THEN // Check if root node
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.172.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( t5 == 0 ), true, Asm000063, Asm000061, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
70.25.172.1.70.25.172.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0002B4 631A0F00 BNE t5, 0, Asm000061
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 000F1A63 [BIG ENDIAN]
Source 1 Register...... 30
Source 2 Register...... 0
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 000002C8 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
70.25.172.1.70.25.172.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0002B8 Asm000063 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.172.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.173 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0002B8 23307500 SD t2, 0[a0] // Update header
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00753023 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 10
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 70.25.174 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__EXTBB t0, t0 // Keep only balance bits
Macro [AVL.__EXTBB] source location is [JAR: /arch/RISCV/macros/Avl.__extbb.mac]
70.25.174.1 ALNC:AVL.__EXTBB|AVL.INSERT:AVL.__BALNC:AVL.__EXTBB 0002BC 93F23200 ANDI t0, 0b011[t0] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0032F293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
70.25.175 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0002C0 23B45300 SD t0, 8+0[t2] // Store it back
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0053B423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 7
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.176 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC BREAK // Done - root node
Macro [BREAK] source location is [JAR: /arch/RISCV/macros/Break.mac]
70.25.176.1 VL.__BALNC:BREAK|AVL.INSERT:AVL.__BALNC:BREAK 0002C4 6F00C001 JAL Asm000017
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 01C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00001C [HEX]
Immediate Sect. Offset.... 000002E0 [HEX]
Immediate Encoded......... 0_00000000_0_0000001110 [BIN] Bits [20:1]
[+][-] 70.25.177 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.177.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 0002C8 Asm000061 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.177.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 0002C8 Asm000062 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.177.3 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.178 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC
70.25.179 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0002C8 23B45300 SD t0,8+0[t2] // Store parent field in node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0053B423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 7
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 70.25.180 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC AVL.__EXTLT t6, t0 // Get parent link type of A node
Macro [AVL.__EXTLT] source location is [JAR: /arch/RISCV/macros/Avl.__extlt.mac]
70.25.180.1 ALNC:AVL.__EXTLT|AVL.INSERT:AVL.__BALNC:AVL.__EXTLT 0002CC 93FF4200 ANDI t6, 0b100[t0] // Extract parent node link type
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0042FF93 [BIG ENDIAN]
Destination Register...... 31
Source 1 Register...... 5
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
[+][-] 70.25.181 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC IF ( t6 > 0 ), THEN // Check if left link
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 70.25.181.1 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF __CondGen ( t6 > 0 ), true, Asm000066, Asm000064, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 70.25.181.1.70.25.181.1.1 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN BLE t6, 0, Asm000064
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
70.25.181.1.70.25.181.1.1.1 IF:__CONDGEN:BLE|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN:BLE 0002D0 6356F001 BGE 0, t6, Asm000064
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 01F05663 [BIG ENDIAN]
Source 1 Register...... 0
Source 2 Register...... 31
Immediate PCRel........... 00C [HEX]
Immediate Sect. Offset.... 000002DC [HEX]
Immediate Bits [12:1]..... 0_0_000000_0110 [BIN] bits [12:1]
70.25.181.1.70.25.181.1.2 LNC:IF:__CONDGEN|AVL.INSERT:AVL.__BALNC:IF:__CONDGEN 0002D4 Asm000066 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.181.2 T:AVL.__BALNC:IF|AVL.INSERT:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.182 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0002D4 23307F00 SD t2, 0[t5] // Set new top node as left child of parent
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 007F3023 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 30
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 70.25.183 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ELSE
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
70.25.183.1 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
70.25.183.2 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE 0002D8 6F008000 JAL Asm000065
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0080006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000008 [HEX]
Immediate Sect. Offset.... 000002E0 [HEX]
Immediate Encoded......... 0_00000000_0_0000000100 [BIN] Bits [20:1]
70.25.183.3 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE 0002DC Asm000064 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.183.4 AVL.__BALNC:ELSE|AVL.INSERT:AVL.__BALNC:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
70.25.184 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC 0002DC 23387F00 SD t2, 16+0[t5] // Set new top node as right child of parent
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 007F3823 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 30
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 70.25.185 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.25.185.1 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF 0002E0 Asm000065 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.185.2 VL.__BALNC:ENDIF|AVL.INSERT:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 70.25.186 SERT:AVL.__BALNC|AVL.INSERT:AVL.__BALNC ENDDO // ENd of balance block
Macro [ENDDO] source location is [JAR: /arch/RISCV/macros/Enddo.mac]
70.25.186.1 VL.__BALNC:ENDDO|AVL.INSERT:AVL.__BALNC:ENDDO 0002E0 Asm000017 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.25.186.2 VL.__BALNC:ENDDO|AVL.INSERT:AVL.__BALNC:ENDDO INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 70.26 |AVL.INSERT ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
70.26.1 AVL.INSERT:ENDIF|AVL.INSERT:ENDIF 0002E0 Asm000003 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
70.26.2 AVL.INSERT:ENDIF|AVL.INSERT:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
71 | // Invoke AVL.INSERT macro
[+][-] 72 | EXIT // Return to caller
Macro [EXIT] source location is [JAR: /arch/RISCV/macros/Exit.mac]
72.1 |EXIT 0002E0 67800000 JALR 0, 0[ra] // Return to caller
JALR: Jump to ( Reg1 + immediate ) address, and store link address in RegD
Machine Instruction....... 00008067 [BIG ENDIAN]
Destination Register...... 0
Source 1 Register...... 1
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
73 | //
74 | 0002E4 1305F0FF duplKey ADDI a0, -1[0] // Duplicate key handler
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF00513 [BIG ENDIAN]
Destination Register...... 10
Source 1 Register...... 0
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
[+][-] 75 | EXIT // Return -1 to caller
Macro [EXIT] source location is [JAR: /arch/RISCV/macros/Exit.mac]
75.1 |EXIT 0002E8 67800000 JALR 0, 0[ra] // Return to caller
JALR: Jump to ( Reg1 + immediate ) address, and store link address in RegD
Machine Instruction....... 00008067 [BIG ENDIAN]
Destination Register...... 0
Source 1 Register...... 1
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
76 | //
[+][-] 77 | dvasmavlremove /> Entry label
Macro [ENTRY] source location is [JAR: /arch/RISCV/macros/Entry.mac]
78 | ENTRY Stack=!"" // Leaf entry, only A* and T* registers
78.1 |ENTRY EXPORT dvasmavlremove
78.2 |ENTRY 0002F0 dvasmavlremove DWRD 0[0]
ABSOLUTE, alignment [8], length [8], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 0000000000000000
Code [BIG ENDIAN] -> 0000000000000000
Code [DECIMAL ] -> 0
79 | // are used. No need to use a stack
80 | // or save/restore registers
[+][-] 81 | AVL.REMOVE 0[A0], A1, [A2-6,T0-2] // Invoke AVL.REMOVE macro
Macro [AVL.REMOVE] source location is [JAR: /arch/RISCV/macros/Avl.remove.mac]
[+][-] 81.1 |AVL.REMOVE DO // Start main DO loop
Macro [DO] source location is [JAR: /arch/RISCV/macros/Do.mac]
81.1.1 |AVL.REMOVE:DO 0002F0 Asm000068 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.1.2 |AVL.REMOVE:DO INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.2 |AVL.REMOVE 0002F0 83B60500 LD A3, 0[A1] // Load left child addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0005B683 [BIG ENDIAN]
Destination Register...... 13
Source 1 Register...... 11
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
81.3 |AVL.REMOVE 0002F4 03B68500 LD A2, 8+0[A1] // Load parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0085B603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 11
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.4 |AVL.REMOVE AVL.__EXTPA A4, A2 // Get parent addr
Macro [AVL.__EXTPA] source location is [JAR: /arch/RISCV/macros/Avl.__extpa.mac]
81.4.1 MOVE:AVL.__EXTPA|AVL.REMOVE:AVL.__EXTPA 0002F8 137786FF ANDI A4, ~ 0b111[A2] // Extract parent node addr from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF867713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 12
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 81.5 |AVL.REMOVE AVL.__EXTLT A6, A2 // Get parent link type
Macro [AVL.__EXTLT] source location is [JAR: /arch/RISCV/macros/Avl.__extlt.mac]
81.5.1 MOVE:AVL.__EXTLT|AVL.REMOVE:AVL.__EXTLT 0002FC 13784600 ANDI A6, 0b100[A2] // Extract parent node link type
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00467813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 12
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
81.6 |AVL.REMOVE 000300 83B70501 LD A5, 16+0[A1] // Load left child addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0105B783 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 11
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
81.7 |AVL.REMOVE
81.7 |AVL.REMOVE //
81.8 |AVL.REMOVE // Node is leaf
81.9 |AVL.REMOVE //
[+][-] 81.11 |AVL.REMOVE IF ( A3 == 0 && A5 == 0 ), THEN // Handle leaf node
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.11.1 |AVL.REMOVE:IF __CondGen ( A3 == 0 && A5 == 0 ), true, Asm000072, Asm000070, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.11.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000304 63940602 BNE A3, 0, Asm000070
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 02069463 [BIG ENDIAN]
Source 1 Register...... 13
Source 2 Register...... 0
Immediate PCRel........... 028 [HEX]
Immediate Sect. Offset.... 0000032C [HEX]
Immediate Bits [12:1]..... 0_0_000001_0100 [BIN] bits [12:1]
81.11.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000308 63920702 BNE A5, 0, Asm000070
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 02079263 [BIG ENDIAN]
Source 1 Register...... 15
Source 2 Register...... 0
Immediate PCRel........... 024 [HEX]
Immediate Sect. Offset.... 0000032C [HEX]
Immediate Bits [12:1]..... 0_0_000001_0010 [BIN] bits [12:1]
81.11.1.3 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 00030C Asm000072 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.11.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.12 |AVL.REMOVE
[+][-] 81.13 |AVL.REMOVE IF ( A4 == 0 ), THEN // Node is root and leaf
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.13.1 |AVL.REMOVE:IF __CondGen ( A4 == 0 ), true, Asm000075, Asm000073, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.13.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 00030C 63160700 BNE A4, 0, Asm000073
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00071663 [BIG ENDIAN]
Source 1 Register...... 14
Source 2 Register...... 0
Immediate PCRel........... 00C [HEX]
Immediate Sect. Offset.... 00000318 [HEX]
Immediate Bits [12:1]..... 0_0_000000_0110 [BIN] bits [12:1]
81.13.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000310 Asm000075 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.13.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.14 |AVL.REMOVE 000310 23300500 SD 0, 0[A0] // Mark tree as empy
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00053023 [BIG ENDIAN]
Source 2 Register...... 0
Src. 1/Base Register...... 10
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.15 |AVL.REMOVE BREAK // Done - tree is empy
Macro [BREAK] source location is [JAR: /arch/RISCV/macros/Break.mac]
81.15.1 AVL.REMOVE:BREAK|AVL.REMOVE:BREAK 000314 6F00C049 JAL Asm000069
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 49C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00049C [HEX]
Immediate Sect. Offset.... 000007B0 [HEX]
Immediate Encoded......... 0_00000000_0_1001001110 [BIN] Bits [20:1]
[+][-] 81.16 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.16.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000318 Asm000073 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.16.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000318 Asm000074 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.16.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.17 |AVL.REMOVE
[+][-] 81.18 |AVL.REMOVE IF ( A6 != 0 ), THEN // Check if node is left child
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.18.1 |AVL.REMOVE:IF __CondGen ( A6 != 0 ), true, Asm000078, Asm000076, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.18.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000318 63060800 BEQ A6, 0, Asm000076
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00080663 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 00C [HEX]
Immediate Sect. Offset.... 00000324 [HEX]
Immediate Bits [12:1]..... 0_0_000000_0110 [BIN] bits [12:1]
81.18.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 00031C Asm000078 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.18.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.19 |AVL.REMOVE 00031C 23300700 SD 0, 0[A4] // Clear left child addr in parent
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00073023 [BIG ENDIAN]
Source 2 Register...... 0
Src. 1/Base Register...... 14
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.20 |AVL.REMOVE GOTO Asm000067 // Process balancing
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.20.1 |AVL.REMOVE:GOTO 000320 6F00401E JAL 0, Asm000067 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 1E40006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +0001E4 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Encoded......... 0_00000000_0_0011110010 [BIN] Bits [20:1]
[+][-] 81.21 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.21.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000324 Asm000076 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.21.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000324 Asm000077 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.21.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.22 |AVL.REMOVE
81.23 |AVL.REMOVE 000324 23380700 SD 0, 16+0[A4] // Clear right child addr in parent
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00073823 [BIG ENDIAN]
Source 2 Register...... 0
Src. 1/Base Register...... 14
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 81.24 |AVL.REMOVE GOTO Asm000067 // Process balancing
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.24.1 |AVL.REMOVE:GOTO 000328 6F00C01D JAL 0, Asm000067 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 1DC0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +0001DC [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Encoded......... 0_00000000_0_0011101110 [BIN] Bits [20:1]
[+][-] 81.25 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.25.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 00032C Asm000070 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.25.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 00032C Asm000071 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.25.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.26 |AVL.REMOVE
81.26 |AVL.REMOVE //
81.27 |AVL.REMOVE // Node does not have left child
81.28 |AVL.REMOVE //
[+][-] 81.30 |AVL.REMOVE IF ( A3 == 0 ), THEN // Node does not have left child
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.30.1 |AVL.REMOVE:IF __CondGen ( A3 == 0 ), true, Asm000081, Asm000079, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.30.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 00032C 63960604 BNE A3, 0, Asm000079
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 04069663 [BIG ENDIAN]
Source 1 Register...... 13
Source 2 Register...... 0
Immediate PCRel........... 04C [HEX]
Immediate Sect. Offset.... 00000378 [HEX]
Immediate Bits [12:1]..... 0_0_000010_0110 [BIN] bits [12:1]
81.30.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000330 Asm000081 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.30.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.31 |AVL.REMOVE 000330 03B68700 LD A2, 8+0[A5] // Load right child parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0087B603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 15
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
81.32 |AVL.REMOVE
[+][-] 81.33 |AVL.REMOVE IF ( A4 == 0 ), THEN // Check if node is root
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.33.1 |AVL.REMOVE:IF __CondGen ( A4 == 0 ), true, Asm000084, Asm000082, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.33.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000334 631A0700 BNE A4, 0, Asm000082
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00071A63 [BIG ENDIAN]
Source 1 Register...... 14
Source 2 Register...... 0
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 00000348 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
81.33.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000338 Asm000084 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.33.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.34 |AVL.REMOVE 000338 2330F500 SD A5, 0[A0] // Update header
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00F53023 [BIG ENDIAN]
Source 2 Register...... 15
Src. 1/Base Register...... 10
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.35 |AVL.REMOVE AVL.__EXTBB A2, A2 // Keep only balance bits
Macro [AVL.__EXTBB] source location is [JAR: /arch/RISCV/macros/Avl.__extbb.mac]
81.35.1 MOVE:AVL.__EXTBB|AVL.REMOVE:AVL.__EXTBB 00033C 13763600 ANDI A2, 0b011[A2] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.36 |AVL.REMOVE 000340 23B4C700 SD A2, 8+0[A5] // Store it back
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C7B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 15
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.37 |AVL.REMOVE BREAK // Done - right child is new root
Macro [BREAK] source location is [JAR: /arch/RISCV/macros/Break.mac]
81.37.1 AVL.REMOVE:BREAK|AVL.REMOVE:BREAK 000344 6F00C046 JAL Asm000069
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 46C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00046C [HEX]
Immediate Sect. Offset.... 000007B0 [HEX]
Immediate Encoded......... 0_00000000_0_1000110110 [BIN] Bits [20:1]
[+][-] 81.38 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.38.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000348 Asm000082 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.38.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000348 Asm000083 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.38.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.39 |AVL.REMOVE
[+][-] 81.40 |AVL.REMOVE IF ( A6 == 0 ), THEN // Check if right child
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.40.1 |AVL.REMOVE:IF __CondGen ( A6 == 0 ), true, Asm000087, Asm000085, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.40.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000348 631C0800 BNE A6, 0, Asm000085
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00081C63 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 018 [HEX]
Immediate Sect. Offset.... 00000360 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1100 [BIN] bits [12:1]
81.40.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 00034C Asm000087 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.40.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.41 |AVL.REMOVE 00034C 2338F700 SD A5, 16+0[A4] // Node right child is new parent right child
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00F73823 [BIG ENDIAN]
Source 2 Register...... 15
Src. 1/Base Register...... 14
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 81.42 |AVL.REMOVE AVL.__SETPA A5, A2, A2, A4,, RIGHT, CLEAR, 8+0 // Link from new parent is to right child
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.42.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000350 13763600 ANDI A2, 3[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.42.2 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000354 3366E600 OR A2, A4 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00E66633 [BIG ENDIAN]
Destination Register...... 12
Source 2 Register...... 14
Source 1 Register...... 12
81.42.3 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000358 23B4C700 SD A2, 8+0[A5] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C7B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 15
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.43 |AVL.REMOVE GOTO Asm000067 // Process balancing
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.43.1 |AVL.REMOVE:GOTO 00035C 6F00801A JAL 0, Asm000067 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 1A80006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +0001A8 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Encoded......... 0_00000000_0_0011010100 [BIN] Bits [20:1]
[+][-] 81.44 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.44.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000360 Asm000085 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.44.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000360 Asm000086 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.44.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.45 |AVL.REMOVE
81.46 |AVL.REMOVE 000360 2330F700 SD A5, 0[A4] // Node right child is new parent left child
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00F73023 [BIG ENDIAN]
Source 2 Register...... 15
Src. 1/Base Register...... 14
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.47 |AVL.REMOVE AVL.__SETPA A5, A2, A2, A4,, LEFT, CLEAR, 8+0 // Link from new parent is to left child
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.47.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000364 13763600 ANDI A2, 3[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.47.2 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000368 13664600 ORI A2, 4[A2] // Set link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00466613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
81.47.3 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 00036C 3366E600 OR A2, A4 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00E66633 [BIG ENDIAN]
Destination Register...... 12
Source 2 Register...... 14
Source 1 Register...... 12
81.47.4 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000370 23B4C700 SD A2, 8+0[A5] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C7B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 15
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.48 |AVL.REMOVE GOTO Asm000067 // Process balancing
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.48.1 |AVL.REMOVE:GOTO 000374 6F000019 JAL 0, Asm000067 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 1900006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000190 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Encoded......... 0_00000000_0_0011001000 [BIN] Bits [20:1]
[+][-] 81.49 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.49.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000378 Asm000079 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.49.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000378 Asm000080 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.49.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.50 |AVL.REMOVE
81.50 |AVL.REMOVE //
81.51 |AVL.REMOVE // Node does not have right child
81.52 |AVL.REMOVE //
[+][-] 81.54 |AVL.REMOVE IF ( A5 == 0 ), THEN // Node does not have right child
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.54.1 |AVL.REMOVE:IF __CondGen ( A5 == 0 ), true, Asm000090, Asm000088, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.54.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000378 63960704 BNE A5, 0, Asm000088
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 04079663 [BIG ENDIAN]
Source 1 Register...... 15
Source 2 Register...... 0
Immediate PCRel........... 04C [HEX]
Immediate Sect. Offset.... 000003C4 [HEX]
Immediate Bits [12:1]..... 0_0_000010_0110 [BIN] bits [12:1]
81.54.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 00037C Asm000090 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.54.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.55 |AVL.REMOVE 00037C 03B68600 LD A2, 8+0[A3] // Load left child parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0086B603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 13
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
81.56 |AVL.REMOVE
[+][-] 81.57 |AVL.REMOVE IF ( A4 == 0 ), THEN // Check if node is root
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.57.1 |AVL.REMOVE:IF __CondGen ( A4 == 0 ), true, Asm000093, Asm000091, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.57.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000380 631A0700 BNE A4, 0, Asm000091
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00071A63 [BIG ENDIAN]
Source 1 Register...... 14
Source 2 Register...... 0
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 00000394 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
81.57.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000384 Asm000093 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.57.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.58 |AVL.REMOVE 000384 2330D500 SD A3, 0[A0] // Update header
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00D53023 [BIG ENDIAN]
Source 2 Register...... 13
Src. 1/Base Register...... 10
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.59 |AVL.REMOVE AVL.__EXTBB A2, A2 // Keep only balance bits
Macro [AVL.__EXTBB] source location is [JAR: /arch/RISCV/macros/Avl.__extbb.mac]
81.59.1 MOVE:AVL.__EXTBB|AVL.REMOVE:AVL.__EXTBB 000388 13763600 ANDI A2, 0b011[A2] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.60 |AVL.REMOVE 00038C 23B4C600 SD A2, 8+0[A3] // Store it back
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C6B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 13
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.61 |AVL.REMOVE BREAK // Done - left child is new root
Macro [BREAK] source location is [JAR: /arch/RISCV/macros/Break.mac]
81.61.1 AVL.REMOVE:BREAK|AVL.REMOVE:BREAK 000390 6F000042 JAL Asm000069
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 4200006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000420 [HEX]
Immediate Sect. Offset.... 000007B0 [HEX]
Immediate Encoded......... 0_00000000_0_1000010000 [BIN] Bits [20:1]
[+][-] 81.62 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.62.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000394 Asm000091 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.62.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000394 Asm000092 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.62.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.63 |AVL.REMOVE
[+][-] 81.64 |AVL.REMOVE IF ( A6 != 0 ), THEN // Check if node is left child
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.64.1 |AVL.REMOVE:IF __CondGen ( A6 != 0 ), true, Asm000096, Asm000094, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.64.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000394 630E0800 BEQ A6, 0, Asm000094
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00080E63 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 01C [HEX]
Immediate Sect. Offset.... 000003B0 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1110 [BIN] bits [12:1]
81.64.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000398 Asm000096 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.64.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.65 |AVL.REMOVE 000398 2330D700 SD A3, 0[A4] // Node left child is new parent left child
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00D73023 [BIG ENDIAN]
Source 2 Register...... 13
Src. 1/Base Register...... 14
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.66 |AVL.REMOVE AVL.__SETPA A3, A2, A2, A4,, LEFT, CLEAR, 8+0 // Link from new parent is to left child
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.66.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 00039C 13763600 ANDI A2, 3[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.66.2 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0003A0 13664600 ORI A2, 4[A2] // Set link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00466613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
81.66.3 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0003A4 3366E600 OR A2, A4 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00E66633 [BIG ENDIAN]
Destination Register...... 12
Source 2 Register...... 14
Source 1 Register...... 12
81.66.4 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0003A8 23B4C600 SD A2, 8+0[A3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C6B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 13
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.67 |AVL.REMOVE GOTO Asm000067 // Process balancing
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.67.1 |AVL.REMOVE:GOTO 0003AC 6F008015 JAL 0, Asm000067 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 1580006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000158 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Encoded......... 0_00000000_0_0010101100 [BIN] Bits [20:1]
[+][-] 81.68 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.68.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 0003B0 Asm000094 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.68.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 0003B0 Asm000095 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.68.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.69 |AVL.REMOVE
81.70 |AVL.REMOVE 0003B0 2338D700 SD A3, 16+0[A4] // Node left child is new parent right child
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00D73823 [BIG ENDIAN]
Source 2 Register...... 13
Src. 1/Base Register...... 14
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 81.71 |AVL.REMOVE AVL.__SETPA A3, A2, A2, A4,, RIGHT, CLEAR, 8+0 // Link from new parent is to right child
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.71.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0003B4 13763600 ANDI A2, 3[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.71.2 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0003B8 3366E600 OR A2, A4 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00E66633 [BIG ENDIAN]
Destination Register...... 12
Source 2 Register...... 14
Source 1 Register...... 12
81.71.3 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0003BC 23B4C600 SD A2, 8+0[A3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C6B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 13
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.72 |AVL.REMOVE GOTO Asm000067 // Process balancing
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.72.1 |AVL.REMOVE:GOTO 0003C0 6F004014 JAL 0, Asm000067 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 1440006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000144 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Encoded......... 0_00000000_0_0010100010 [BIN] Bits [20:1]
[+][-] 81.73 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.73.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 0003C4 Asm000088 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.73.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 0003C4 Asm000089 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.73.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.74 |AVL.REMOVE
81.74 |AVL.REMOVE //
81.75 |AVL.REMOVE // Node has both left and right child
81.76 |AVL.REMOVE //
[+][-] 81.78 |AVL.REMOVE AVL.__EXTBB T0, A2 // Get balance bits
Macro [AVL.__EXTBB] source location is [JAR: /arch/RISCV/macros/Avl.__extbb.mac]
81.78.1 MOVE:AVL.__EXTBB|AVL.REMOVE:AVL.__EXTBB 0003C4 93723600 ANDI T0, 0b011[A2] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.79 |AVL.REMOVE
81.79 |AVL.REMOVE //
81.80 |AVL.REMOVE // Use left subtree
81.81 |AVL.REMOVE //
[+][-] 81.83 |AVL.REMOVE IF ( T0 != 0 ), THEN // Use left subtree since it is deeper or even
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.83.1 |AVL.REMOVE:IF __CondGen ( T0 != 0 ), true, Asm000099, Asm000097, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.83.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0003C8 6380020A BEQ T0, 0, Asm000097
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 0A028063 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 0
Immediate PCRel........... 0A0 [HEX]
Immediate Sect. Offset.... 00000468 [HEX]
Immediate Bits [12:1]..... 0_0_000101_0000 [BIN] bits [12:1]
81.83.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0003CC Asm000099 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.83.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.84 |AVL.REMOVE MV T2, A3 // Copy left child to prime the loop
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.84.1 |AVL.REMOVE:MV 0003CC 93830600 ADDI T2, 0[A3]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00068393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 13
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.85 |AVL.REMOVE WHILE // Start loop to find right most node in subtree
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
81.85.1 AVL.REMOVE:WHILE|AVL.REMOVE:WHILE 0003D0 Asm000100 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.85.2 AVL.REMOVE:WHILE|AVL.REMOVE:WHILE 0003D0 Asm000101 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.85.3 AVL.REMOVE:WHILE|AVL.REMOVE:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.86 |AVL.REMOVE 0003D0 83B20301 LD T0, 16+0[T2] // Load right child addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0103B283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 7
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
[+][-] 81.87 |AVL.REMOVE IF ( T0 == 0 ), BREAK // Most right node in left subtree found
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.87.1 |AVL.REMOVE:IF __CondGen ( T0 == 0 ), false, Asm000102, Asm000103, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.87.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0003D4 63860200 BEQ T0, 0, Asm000102
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00028663 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 0
Immediate PCRel........... 00C [HEX]
Immediate Sect. Offset.... 000003E0 [HEX]
Immediate Bits [12:1]..... 0_0_000000_0110 [BIN] bits [12:1]
81.87.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0003D8 Asm000103 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 81.88 |AVL.REMOVE MV T2, T0 // Copy node addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.88.1 |AVL.REMOVE:MV 0003D8 93830200 ADDI T2, 0[T0]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00028393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 5
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.89 |AVL.REMOVE ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
81.89.1 .REMOVE:ENDWHILE|AVL.REMOVE:ENDWHILE 0003DC 6FF05FFF JAL Asm000101
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... FF5FF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -00000C [HEX]
Immediate Sect. Offset.... 000003D0 [HEX]
Immediate Encoded......... 1_11111111_1_1111111010 [BIN] Bits [20:1]
81.89.2 .REMOVE:ENDWHILE|AVL.REMOVE:ENDWHILE 0003E0 Asm000102 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.89.3 .REMOVE:ENDWHILE|AVL.REMOVE:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.90 |AVL.REMOVE
[+][-] 81.91 |AVL.REMOVE IF ( A4 == 0 ), THEN // Check if node is root
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.91.1 |AVL.REMOVE:IF __CondGen ( A4 == 0 ), true, Asm000106, Asm000104, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.91.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0003E0 63160700 BNE A4, 0, Asm000104
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00071663 [BIG ENDIAN]
Source 1 Register...... 14
Source 2 Register...... 0
Immediate PCRel........... 00C [HEX]
Immediate Sect. Offset.... 000003EC [HEX]
Immediate Bits [12:1]..... 0_0_000000_0110 [BIN] bits [12:1]
81.91.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0003E4 Asm000106 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.91.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.92 |AVL.REMOVE 0003E4 23307500 SD T2, 0[A0] // Update header addr of root node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00753023 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 10
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.93 |AVL.REMOVE ELSE
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
81.93.1 |AVL.REMOVE:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.93.2 |AVL.REMOVE:ELSE 0003E8 6F004001 JAL Asm000105
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0140006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000014 [HEX]
Immediate Sect. Offset.... 000003FC [HEX]
Immediate Encoded......... 0_00000000_0_0000001010 [BIN] Bits [20:1]
81.93.3 |AVL.REMOVE:ELSE 0003EC Asm000104 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.93.4 |AVL.REMOVE:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.94 |AVL.REMOVE IF ( A6 == 0 ), THEN // Check if parent link type is right
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.94.1 |AVL.REMOVE:IF __CondGen ( A6 == 0 ), true, Asm000109, Asm000107, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.94.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0003EC 63160800 BNE A6, 0, Asm000107
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00081663 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 00C [HEX]
Immediate Sect. Offset.... 000003F8 [HEX]
Immediate Bits [12:1]..... 0_0_000000_0110 [BIN] bits [12:1]
81.94.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0003F0 Asm000109 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.94.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.95 |AVL.REMOVE 0003F0 23387700 SD T2, 16+0[A4] // Update parent right child addr
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00773823 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 14
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 81.96 |AVL.REMOVE ELSE
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
81.96.1 |AVL.REMOVE:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.96.2 |AVL.REMOVE:ELSE 0003F4 6F008000 JAL Asm000108
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0080006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000008 [HEX]
Immediate Sect. Offset.... 000003FC [HEX]
Immediate Encoded......... 0_00000000_0_0000000100 [BIN] Bits [20:1]
81.96.3 |AVL.REMOVE:ELSE 0003F8 Asm000107 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.96.4 |AVL.REMOVE:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.97 |AVL.REMOVE 0003F8 23307700 SD T2, 0[A4] // Update parent left child addr
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00773023 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 14
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.98 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.98.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 0003FC Asm000108 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.98.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 81.99 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.99.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 0003FC Asm000105 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.99.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.100 |AVL.REMOVE
81.101 |AVL.REMOVE 0003FC 83B28300 LD T0, 8+0[T2] // Get replace node parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0083B283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 7
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
81.102 |AVL.REMOVE 000400 03B30300 LD T1, 0[T2] // Get left child addr if any
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0003B303 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 7
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
81.103 |AVL.REMOVE 000404 23B4C300 SD A2, 8+0[T2] // Store parent field in replace node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C3B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 7
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
81.104 |AVL.REMOVE 000408 23B8F300 SD A5, 16+0[T2] // Store right child addr in replace node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00F3B823 [BIG ENDIAN]
Source 2 Register...... 15
Src. 1/Base Register...... 7
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
81.105 |AVL.REMOVE 00040C 03B88700 LD A6, 8+0[A5] // Get parent field of right node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0087B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 15
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.106 |AVL.REMOVE AVL.__SETPA A5, A6, A6, T2,,, CLEAR, 8+0 // Replace parent addr in right child parent field
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.106.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000410 13787800 ANDI A6, 7[A6] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00787813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. +007 [HEX]
Immediate Encoded......... 000000000111 [BIN] Bits [11:0]
81.106.2 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000414 33687800 OR A6, T2 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00786833 [BIG ENDIAN]
Destination Register...... 16
Source 2 Register...... 7
Source 1 Register...... 16
81.106.3 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000418 23B40701 SD A6, 8+0[A5] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0107B423 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 15
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
81.107 |AVL.REMOVE
[+][-] 81.108 |AVL.REMOVE IF ( A3 != T2 ), THEN // Check if replace node is not left child of node
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.108.1 |AVL.REMOVE:IF __CondGen ( A3 != T2 ), true, Asm000112, Asm000110, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.108.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 00041C 638E7602 BEQ A3, T2, Asm000110
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 02768E63 [BIG ENDIAN]
Source 1 Register...... 13
Source 2 Register...... 7
Immediate PCRel........... 03C [HEX]
Immediate Sect. Offset.... 00000458 [HEX]
Immediate Bits [12:1]..... 0_0_000001_1110 [BIN] bits [12:1]
81.108.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000420 Asm000112 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.108.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.109 |AVL.REMOVE 000420 23B0D300 SD A3, 0[T2] // Set left child for replacement node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00D3B023 [BIG ENDIAN]
Source 2 Register...... 13
Src. 1/Base Register...... 7
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
81.110 |AVL.REMOVE 000424 03B88600 LD A6, 8+0[A3] // Get parent field of left node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0086B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 13
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.111 |AVL.REMOVE AVL.__SETPA A3, A6, A6, T2,,, CLEAR, 8+0 // Replace parent addr in parent field of left child
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.111.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000428 13787800 ANDI A6, 7[A6] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00787813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. +007 [HEX]
Immediate Encoded......... 000000000111 [BIN] Bits [11:0]
81.111.2 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 00042C 33687800 OR A6, T2 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00786833 [BIG ENDIAN]
Destination Register...... 16
Source 2 Register...... 7
Source 1 Register...... 16
81.111.3 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000430 23B40601 SD A6, 8+0[A3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0106B423 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 13
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.112 |AVL.REMOVE AVL.__EXTPA A4, T0 // Get parent addr of replace node
Macro [AVL.__EXTPA] source location is [JAR: /arch/RISCV/macros/Avl.__extpa.mac]
81.112.1 MOVE:AVL.__EXTPA|AVL.REMOVE:AVL.__EXTPA 000434 13F782FF ANDI A4, ~ 0b111[T0] // Extract parent node addr from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF82F713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 5
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
81.113 |AVL.REMOVE 000438 23386700 SD T1, 16+0[A4] // Store right child addr of replace node parent
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00673823 [BIG ENDIAN]
Source 2 Register...... 6
Src. 1/Base Register...... 14
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 81.114 |AVL.REMOVE AVL.__SETPA , A2, A4,,, RIGHT, NOCLEAR, 8+0 // Set parent link to right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
[+][-] 81.114.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA MV A2, A4 // Copy parent field - Set link bits
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.114.1.1 E:AVL.__SETPA:MV|AVL.REMOVE:AVL.__SETPA:MV 00043C 13060700 ADDI A2, 0[A4]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00070613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 14
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.115 |AVL.REMOVE IF ( T1 == 0 ), GOTO, ID= Asm000067 // Process balancing
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.115.1 |AVL.REMOVE:IF __CondGen ( T1 == 0 ), false, Asm000067, Asm000113, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.115.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000440 6302030C BEQ T1, 0, Asm000067
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 0C030263 [BIG ENDIAN]
Source 1 Register...... 6
Source 2 Register...... 0
Immediate PCRel........... 0C4 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Bits [12:1]..... 0_0_000110_0010 [BIN] bits [12:1]
81.115.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000444 Asm000113 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.116 |AVL.REMOVE 000444 03368300 LD A2, 8+0[T1] // Get parent field of replace node left child
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00833603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 6
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.117 |AVL.REMOVE AVL.__SETPA T1, A2, A2, A4,, RIGHT, CLEAR, 8+0 // Replace parent addr in replace node left child
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.117.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000448 13763600 ANDI A2, 3[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.117.2 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 00044C 3366E600 OR A2, A4 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00E66633 [BIG ENDIAN]
Destination Register...... 12
Source 2 Register...... 14
Source 1 Register...... 12
81.117.3 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000450 2334C300 SD A2, 8+0[T1] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C33423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 6
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.118 |AVL.REMOVE GOTO Asm000067 // Process balancing
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.118.1 |AVL.REMOVE:GOTO 000454 6F00000B JAL 0, Asm000067 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0B00006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +0000B0 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Encoded......... 0_00000000_0_0001011000 [BIN] Bits [20:1]
[+][-] 81.119 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.119.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000458 Asm000110 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.119.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000458 Asm000111 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.119.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.120 |AVL.REMOVE
[+][-] 81.121 |AVL.REMOVE AVL.__SETPA , A2, T2,,, LEFT, NOCLEAR, 8+0 // Set parent link to replace node to left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.121.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 000458 13E64300 ORI A2, 4[T2] // Set link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0043E613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 7
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
[+][-] 81.122 |AVL.REMOVE IF ( T1 == 0 ), GOTO, ID= Asm000067 // Process balancing
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.122.1 |AVL.REMOVE:IF __CondGen ( T1 == 0 ), false, Asm000067, Asm000114, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.122.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 00045C 6304030A BEQ T1, 0, Asm000067
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 0A030463 [BIG ENDIAN]
Source 1 Register...... 6
Source 2 Register...... 0
Immediate PCRel........... 0A8 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Bits [12:1]..... 0_0_000101_0100 [BIN] bits [12:1]
81.122.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000460 Asm000114 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.123 |AVL.REMOVE 000460 03368300 LD A2, 8+0[T1] // Get parent field of replace node left child
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00833603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 6
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.124 |AVL.REMOVE GOTO Asm000067 // Process balancing
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.124.1 |AVL.REMOVE:GOTO 000464 6F00000A JAL 0, Asm000067 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0A00006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +0000A0 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Encoded......... 0_00000000_0_0001010000 [BIN] Bits [20:1]
[+][-] 81.125 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.125.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000468 Asm000097 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.125.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000468 Asm000098 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.125.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.126 |AVL.REMOVE
81.126 |AVL.REMOVE //
81.127 |AVL.REMOVE // Use right subtree
81.128 |AVL.REMOVE //
[+][-] 81.130 |AVL.REMOVE MV T2, A5 // Copy right child to prime the loop
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.130.1 |AVL.REMOVE:MV 000468 93830700 ADDI T2, 0[A5]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00078393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.131 |AVL.REMOVE WHILE // Start loop to find right most node in subtree
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
81.131.1 AVL.REMOVE:WHILE|AVL.REMOVE:WHILE 00046C Asm000115 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.131.2 AVL.REMOVE:WHILE|AVL.REMOVE:WHILE 00046C Asm000116 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.131.3 AVL.REMOVE:WHILE|AVL.REMOVE:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.132 |AVL.REMOVE 00046C 83B20300 LD T0, 0[T2] // Load left child addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0003B283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 7
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.133 |AVL.REMOVE IF ( T0 == 0 ), BREAK // Most left node in right subtree found
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.133.1 |AVL.REMOVE:IF __CondGen ( T0 == 0 ), false, Asm000117, Asm000118, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.133.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000470 63860200 BEQ T0, 0, Asm000117
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00028663 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 0
Immediate PCRel........... 00C [HEX]
Immediate Sect. Offset.... 0000047C [HEX]
Immediate Bits [12:1]..... 0_0_000000_0110 [BIN] bits [12:1]
81.133.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000474 Asm000118 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 81.134 |AVL.REMOVE MV T2, T0 // Copy node addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.134.1 |AVL.REMOVE:MV 000474 93830200 ADDI T2, 0[T0]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00028393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 5
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.135 |AVL.REMOVE ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
81.135.1 .REMOVE:ENDWHILE|AVL.REMOVE:ENDWHILE 000478 6FF05FFF JAL Asm000116
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... FF5FF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -00000C [HEX]
Immediate Sect. Offset.... 0000046C [HEX]
Immediate Encoded......... 1_11111111_1_1111111010 [BIN] Bits [20:1]
81.135.2 .REMOVE:ENDWHILE|AVL.REMOVE:ENDWHILE 00047C Asm000117 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.135.3 .REMOVE:ENDWHILE|AVL.REMOVE:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.136 |AVL.REMOVE
[+][-] 81.137 |AVL.REMOVE IF ( A4 == 0 ), THEN // Check if node is root
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.137.1 |AVL.REMOVE:IF __CondGen ( A4 == 0 ), true, Asm000121, Asm000119, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.137.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 00047C 63160700 BNE A4, 0, Asm000119
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00071663 [BIG ENDIAN]
Source 1 Register...... 14
Source 2 Register...... 0
Immediate PCRel........... 00C [HEX]
Immediate Sect. Offset.... 00000488 [HEX]
Immediate Bits [12:1]..... 0_0_000000_0110 [BIN] bits [12:1]
81.137.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000480 Asm000121 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.137.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.138 |AVL.REMOVE 000480 23307500 SD T2, 0[A0] // Update header addr of root node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00753023 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 10
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.139 |AVL.REMOVE ELSE
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
81.139.1 |AVL.REMOVE:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.139.2 |AVL.REMOVE:ELSE 000484 6F004001 JAL Asm000120
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0140006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000014 [HEX]
Immediate Sect. Offset.... 00000498 [HEX]
Immediate Encoded......... 0_00000000_0_0000001010 [BIN] Bits [20:1]
81.139.3 |AVL.REMOVE:ELSE 000488 Asm000119 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.139.4 |AVL.REMOVE:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.140 |AVL.REMOVE IF ( A6 != 0 ), THEN // Check if parent link type is left
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.140.1 |AVL.REMOVE:IF __CondGen ( A6 != 0 ), true, Asm000124, Asm000122, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.140.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000488 63060800 BEQ A6, 0, Asm000122
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00080663 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 00C [HEX]
Immediate Sect. Offset.... 00000494 [HEX]
Immediate Bits [12:1]..... 0_0_000000_0110 [BIN] bits [12:1]
81.140.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 00048C Asm000124 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.140.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.141 |AVL.REMOVE 00048C 23307700 SD T2, 0[A4] // Update parent left child addr
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00773023 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 14
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.142 |AVL.REMOVE ELSE
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
81.142.1 |AVL.REMOVE:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.142.2 |AVL.REMOVE:ELSE 000490 6F008000 JAL Asm000123
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0080006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000008 [HEX]
Immediate Sect. Offset.... 00000498 [HEX]
Immediate Encoded......... 0_00000000_0_0000000100 [BIN] Bits [20:1]
81.142.3 |AVL.REMOVE:ELSE 000494 Asm000122 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.142.4 |AVL.REMOVE:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.143 |AVL.REMOVE 000494 23387700 SD T2, 16+0[A4] // Update parent right child addr
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00773823 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 14
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 81.144 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.144.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000498 Asm000123 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.144.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 81.145 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.145.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 000498 Asm000120 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.145.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.146 |AVL.REMOVE
81.147 |AVL.REMOVE 000498 83B28300 LD T0, 8+0[T2] // Get replace node parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0083B283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 7
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
81.148 |AVL.REMOVE 00049C 03B30301 LD T1, 16+0[T2] // Get right child addr if any
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0103B303 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 7
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
81.149 |AVL.REMOVE 0004A0 23B4C300 SD A2, 8+0[T2] // Store parent field in replace node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C3B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 7
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
81.150 |AVL.REMOVE 0004A4 23B0D300 SD A3, 0[T2] // Store left child addr in replace node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00D3B023 [BIG ENDIAN]
Source 2 Register...... 13
Src. 1/Base Register...... 7
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
81.151 |AVL.REMOVE 0004A8 03B88600 LD A6, 8+0[A3] // Get parent field of left node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0086B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 13
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.152 |AVL.REMOVE AVL.__SETPA A3, A6, A6, T2,,, CLEAR, 8+0 // Replace parent addr in left child parent field
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.152.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0004AC 13787800 ANDI A6, 7[A6] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00787813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. +007 [HEX]
Immediate Encoded......... 000000000111 [BIN] Bits [11:0]
81.152.2 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0004B0 33687800 OR A6, T2 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00786833 [BIG ENDIAN]
Destination Register...... 16
Source 2 Register...... 7
Source 1 Register...... 16
81.152.3 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0004B4 23B40601 SD A6, 8+0[A3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0106B423 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 13
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
81.153 |AVL.REMOVE
[+][-] 81.154 |AVL.REMOVE IF ( A5 != T2 ), THEN // Check if replace node is not right child of node
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.154.1 |AVL.REMOVE:IF __CondGen ( A5 != T2 ), true, Asm000127, Asm000125, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.154.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0004B8 63807704 BEQ A5, T2, Asm000125
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 04778063 [BIG ENDIAN]
Source 1 Register...... 15
Source 2 Register...... 7
Immediate PCRel........... 040 [HEX]
Immediate Sect. Offset.... 000004F8 [HEX]
Immediate Bits [12:1]..... 0_0_000010_0000 [BIN] bits [12:1]
81.154.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0004BC Asm000127 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.154.2 |AVL.REMOVE:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.155 |AVL.REMOVE 0004BC 23B8F300 SD A5, 16+0[T2] // Set right child for replacement node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00F3B823 [BIG ENDIAN]
Source 2 Register...... 15
Src. 1/Base Register...... 7
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
81.156 |AVL.REMOVE 0004C0 03B88700 LD A6, 8+0[A5] // Get parent field of right node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0087B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 15
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.157 |AVL.REMOVE AVL.__SETPA A5, A6, A6, T2,,, CLEAR, 8+0 // Replace parent addr in parent field of right child
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.157.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0004C4 13787800 ANDI A6, 7[A6] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00787813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. +007 [HEX]
Immediate Encoded......... 000000000111 [BIN] Bits [11:0]
81.157.2 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0004C8 33687800 OR A6, T2 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00786833 [BIG ENDIAN]
Destination Register...... 16
Source 2 Register...... 7
Source 1 Register...... 16
81.157.3 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0004CC 23B40701 SD A6, 8+0[A5] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0107B423 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 15
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.158 |AVL.REMOVE AVL.__EXTPA A4, T0 //Get parent addr of replace node
Macro [AVL.__EXTPA] source location is [JAR: /arch/RISCV/macros/Avl.__extpa.mac]
81.158.1 MOVE:AVL.__EXTPA|AVL.REMOVE:AVL.__EXTPA 0004D0 13F782FF ANDI A4, ~ 0b111[T0] // Extract parent node addr from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF82F713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 5
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
81.159 |AVL.REMOVE
81.160 |AVL.REMOVE 0004D4 23306700 SD T1, 0[A4] // Store left child addr of replace node parent
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00673023 [BIG ENDIAN]
Source 2 Register...... 6
Src. 1/Base Register...... 14
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.161 |AVL.REMOVE AVL.__SETPA , A2, A4,,, LEFT, NOCLEAR, 8+0 // Set parent link to left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.161.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0004D8 13664700 ORI A2, 4[A4] // Set link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00476613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 14
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
[+][-] 81.162 |AVL.REMOVE IF ( T1 == 0 ), GOTO, ID= Asm000067 // Process balancing
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.162.1 |AVL.REMOVE:IF __CondGen ( T1 == 0 ), false, Asm000067, Asm000128, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.162.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0004DC 63040302 BEQ T1, 0, Asm000067
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 02030463 [BIG ENDIAN]
Source 1 Register...... 6
Source 2 Register...... 0
Immediate PCRel........... 028 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Bits [12:1]..... 0_0_000001_0100 [BIN] bits [12:1]
81.162.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0004E0 Asm000128 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.163 |AVL.REMOVE 0004E0 03368300 LD A2, 8+0[T1] // Get parent field of replace node right child
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00833603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 6
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.164 |AVL.REMOVE AVL.__SETPA T1, A2, A2, A4,, LEFT, CLEAR, 8+0 // Replace parent addr in replace node right child
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.164.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0004E4 13763600 ANDI A2, 3[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.164.2 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0004E8 13664600 ORI A2, 4[A2] // Set link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00466613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
81.164.3 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0004EC 3366E600 OR A2, A4 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00E66633 [BIG ENDIAN]
Destination Register...... 12
Source 2 Register...... 14
Source 1 Register...... 12
81.164.4 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA 0004F0 2334C300 SD A2, 8+0[T1] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C33423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 6
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.165 |AVL.REMOVE GOTO Asm000067 // Process balancing
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.165.1 |AVL.REMOVE:GOTO 0004F4 6F000001 JAL 0, Asm000067 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0100006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000010 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Encoded......... 0_00000000_0_0000001000 [BIN] Bits [20:1]
[+][-] 81.166 |AVL.REMOVE ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.166.1 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 0004F8 Asm000125 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.166.2 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF 0004F8 Asm000126 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.166.3 AVL.REMOVE:ENDIF|AVL.REMOVE:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.167 |AVL.REMOVE
[+][-] 81.168 |AVL.REMOVE AVL.__SETPA , A2, T2,,, RIGHT, NOCLEAR, 8+0 // Set parent link to replace node to right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
[+][-] 81.168.1 MOVE:AVL.__SETPA|AVL.REMOVE:AVL.__SETPA MV A2, T2 // Copy parent field - Set link bits
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.168.1.1 E:AVL.__SETPA:MV|AVL.REMOVE:AVL.__SETPA:MV 0004F8 13860300 ADDI A2, 0[T2]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00038613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 7
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.169 |AVL.REMOVE IF ( T1 == 0 ), GOTO, ID= Asm000067 // Process balancing
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.169.1 |AVL.REMOVE:IF __CondGen ( T1 == 0 ), false, Asm000067, Asm000129, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.169.1.1 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 0004FC 63040300 BEQ T1, 0, Asm000067
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00030463 [BIG ENDIAN]
Source 1 Register...... 6
Source 2 Register...... 0
Immediate PCRel........... 008 [HEX]
Immediate Sect. Offset.... 00000504 [HEX]
Immediate Bits [12:1]..... 0_0_000000_0100 [BIN] bits [12:1]
81.169.1.2 OVE:IF:__CONDGEN|AVL.REMOVE:IF:__CONDGEN 000500 Asm000129 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.170 |AVL.REMOVE 000500 03368300 LD A2, 8+0[T1] // Get parent field of replace node left child
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00833603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 6
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
81.171 |AVL.REMOVE
81.171 |AVL.REMOVE //
81.172 |AVL.REMOVE // Balance the tree
81.173 |AVL.REMOVE //
[+][-] 81.175 |AVL.REMOVE Asm000067 AVL.__BALNC REMOVE, 0[A0], A2, 0, [A3,A4,A5,A6,T0,T1,T2]
Macro [AVL.__BALNC] source location is [JAR: /arch/RISCV/macros/Avl.__balnc.mac]
81.175.1 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.2 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC // Balance the tree
81.175.3 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
[+][-] 81.175.4 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC Asm000067 AVL.__EXTPA A4, A2 // Set up parent addr for WHILE loop
Macro [AVL.__EXTPA] source location is [JAR: /arch/RISCV/macros/Avl.__extpa.mac]
81.175.4.1 ALNC:AVL.__EXTPA|AVL.REMOVE:AVL.__BALNC:AVL.__EXTPA 000504 137786FF Asm000067 ANDI A4, ~ 0b111[A2] // Extract parent node addr from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF867713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 12
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
81.175.5 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
[+][-] 81.175.6 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC DO // Start balance loop
Macro [DO] source location is [JAR: /arch/RISCV/macros/Do.mac]
81.175.6.1 E:AVL.__BALNC:DO|AVL.REMOVE:AVL.__BALNC:DO 000508 Asm000131 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.6.2 E:AVL.__BALNC:DO|AVL.REMOVE:AVL.__BALNC:DO INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.175.7 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__EXTLT A6, A2 // Extract link type from parent
Macro [AVL.__EXTLT] source location is [JAR: /arch/RISCV/macros/Avl.__extlt.mac]
81.175.7.1 ALNC:AVL.__EXTLT|AVL.REMOVE:AVL.__BALNC:AVL.__EXTLT 000508 13784600 ANDI A6, 0b100[A2] // Extract parent node link type
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00467813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 12
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
81.175.8 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 00050C 13581800 SRLI A6, 1 // Convert link type
SRLI: Shift Logical Right Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 00185813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
81.175.9 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000510 1308F8FF ADDI A6, -1 // ... to +/- 1 to be subtracted from balance
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF80813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
81.175.10 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000514 03368700 LD A2, 8+0[A4] // Get parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00873603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 14
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.175.11 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__EXTBL T2, A2 // Get balance of parent of deleted node
Macro [AVL.__EXTBL] source location is [JAR: /arch/RISCV/macros/Avl.__extbl.mac]
81.175.11.1 ALNC:AVL.__EXTBL|AVL.REMOVE:AVL.__BALNC:AVL.__EXTBL 000518 93733600 ANDI T2, 0b011[A2] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.11.2 ALNC:AVL.__EXTBL|AVL.REMOVE:AVL.__BALNC:AVL.__EXTBL 00051C 9383F3FF ADDI T2, -1 // Subtract 1 to make it any of -1, 0, 1
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF38393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 7
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
81.175.12 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000520 B3830341 SUB T2, A6 // Add (insert) Subtract (remove) link for new balance
SUB: Subtract Reg2 from Reg1 and store result in RegD
Machine Instruction....... 410383B3 [BIG ENDIAN]
Destination Register...... 7
Source 2 Register...... 16
Source 1 Register...... 7
81.175.13 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.13 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.14 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC // Check if left rotation
81.175.15 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
[+][-] 81.175.17 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC LI A6, 1 // Load compare constant
Macro [LI] source location is [JAR: /arch/RISCV/macros/Li.mac]
81.175.17.1 E:AVL.__BALNC:LI|AVL.REMOVE:AVL.__BALNC:LI 000524 13081000 ADDI A6, 1[0] // Load immediate value
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00100813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 0
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 81.175.18 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( T2 > A6 ), THEN // Handle left substree too high
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.18.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( T2 > A6 ), true, Asm000135, Asm000133, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 81.175.18.1.81.175.18.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN BLE T2, A6, Asm000133
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
81.175.18.1.81.175.18.1.1.1 IF:__CONDGEN:BLE|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN:BLE 000528 63547810 BGE A6, T2, Asm000133
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 10785463 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 7
Immediate PCRel........... 108 [HEX]
Immediate Sect. Offset.... 00000630 [HEX]
Immediate Bits [12:1]..... 0_0_001000_0100 [BIN] bits [12:1]
81.175.18.1.81.175.18.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 00052C Asm000135 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.18.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.19 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 00052C 83360700 LD A3, 0[A4] // Load B node addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00073683 [BIG ENDIAN]
Destination Register...... 13
Source 1 Register...... 14
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
81.175.20 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000530 83B70601 LD A5, 16+0[A3] // Get C node addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0106B783 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 13
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
81.175.21 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000534 83B38600 LD T2, 8+0[A3] // get B node parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0086B383 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 13
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.175.22 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__EXTBL T2, T2 // Get B node balance
Macro [AVL.__EXTBL] source location is [JAR: /arch/RISCV/macros/Avl.__extbl.mac]
81.175.22.1 ALNC:AVL.__EXTBL|AVL.REMOVE:AVL.__BALNC:AVL.__EXTBL 000538 93F33300 ANDI T2, 0b011[T2] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0033F393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 7
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.22.2 ALNC:AVL.__EXTBL|AVL.REMOVE:AVL.__BALNC:AVL.__EXTBL 00053C 9383F3FF ADDI T2, -1 // Subtract 1 to make it any of -1, 0, 1
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF38393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 7
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
81.175.23 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.23 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.24 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC // LL rotation - Top node is A, left child is B, right child of B node is C node if any
81.175.25 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
[+][-] 81.175.27 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( T2 >= 0 ), THEN // LL rotation if >= 0
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.27.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( T2 >= 0 ), true, Asm000138, Asm000136, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.27.1.81.175.27.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000540 63CC0304 BLT T2, 0, Asm000136
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 0403CC63 [BIG ENDIAN]
Source 1 Register...... 7
Source 2 Register...... 0
Immediate PCRel........... 058 [HEX]
Immediate Sect. Offset.... 00000598 [HEX]
Immediate Bits [12:1]..... 0_0_000010_1100 [BIN] bits [12:1]
81.175.27.1.81.175.27.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000544 Asm000138 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.27.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.28 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000544 2330F700 SD A5, 0[A4] // Make C node right child of A node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00F73023 [BIG ENDIAN]
Source 2 Register...... 15
Src. 1/Base Register...... 14
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.175.29 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( A5 != 0 ), THEN // Check if C node exists
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.29.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( A5 != 0 ), true, Asm000141, Asm000139, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.29.1.81.175.29.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000548 638C0700 BEQ A5, 0, Asm000139
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00078C63 [BIG ENDIAN]
Source 1 Register...... 15
Source 2 Register...... 0
Immediate PCRel........... 018 [HEX]
Immediate Sect. Offset.... 00000560 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1100 [BIN] bits [12:1]
81.175.29.1.81.175.29.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 00054C Asm000141 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.29.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.30 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 00054C 03B88700 LD A6, 8+0[A5] // Get parent field of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0087B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 15
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.175.31 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A5, A6, A6, A4,, LEFT, CLEAR, 8+0 // Set C node parent to A node - left link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.31.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000550 13783800 ANDI A6, 3[A6] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00387813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.31.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000554 13684800 ORI A6, 4[A6] // Set link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00486813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
81.175.31.3 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000558 3368E800 OR A6, A4 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00E86833 [BIG ENDIAN]
Destination Register...... 16
Source 2 Register...... 14
Source 1 Register...... 16
81.175.31.4 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 00055C 23B40701 SD A6, 8+0[A5] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0107B423 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 15
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.32 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.32.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000560 Asm000139 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.32.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000560 Asm000140 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.32.3 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 81.175.33 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( T2 != 0 ), THEN // Check if B node balance is not even
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.33.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( T2 != 0 ), true, Asm000144, Asm000142, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.33.1.81.175.33.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000560 638E0300 BEQ T2, 0, Asm000142
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00038E63 [BIG ENDIAN]
Source 1 Register...... 7
Source 2 Register...... 0
Immediate PCRel........... 01C [HEX]
Immediate Sect. Offset.... 0000057C [HEX]
Immediate Bits [12:1]..... 0_0_000000_1110 [BIN] bits [12:1]
81.175.33.1.81.175.33.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000564 Asm000144 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.33.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.175.34 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A4, A6, A3,, EVEN, RIGHT, NOCLEAR, 8+0 // Set balance even - right link for A node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.34.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000564 13E81600 ORI A6, 1[A3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0016E813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 13
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
81.175.34.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000568 23340701 SD A6, 8+0[A4] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01073423 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 14
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.35 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A3, A2, A2,, EVEN,, CLEAR, 8+0 // Set balance even - A node parent for B node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.35.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 00056C 1376C6FF ANDI A2, -4[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC67613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
81.175.35.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000570 13661600 ORI A2, 1[A2] // Set balance bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00166613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
81.175.35.3 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000574 23B4C600 SD A2, 8+0[A3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C6B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 13
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.36 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ELSE
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
81.175.36.1 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.36.2 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE 000578 6F004001 JAL Asm000143
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0140006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000014 [HEX]
Immediate Sect. Offset.... 0000058C [HEX]
Immediate Encoded......... 0_00000000_0_0000001010 [BIN] Bits [20:1]
81.175.36.3 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE 00057C Asm000142 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.36.4 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.175.37 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A4, A6, A3,, PLUS, RIGHT, NOCLEAR, 8+0 // Set balance plus - right link for A node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.37.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 00057C 13E82600 ORI A6, 2[A3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0026E813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 13
Immediate................. +002 [HEX]
Immediate Encoded......... 000000000010 [BIN] Bits [11:0]
81.175.37.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000580 23340701 SD A6, 8+0[A4] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01073423 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 14
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.38 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A3, A2, A2,, MINUS,, CLEAR, 8+0 // Set balance minus for A node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.38.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000584 1376C6FF ANDI A2, -4[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC67613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
81.175.38.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000588 23B4C600 SD A2, 8+0[A3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C6B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 13
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.39 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.39.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 00058C Asm000143 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.39.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.40 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 00058C 23B8E600 SD A4, 16+0[A3] // Set A node as right child of B node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00E6B823 [BIG ENDIAN]
Source 2 Register...... 14
Src. 1/Base Register...... 13
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 81.175.41 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC MV A4, A3 // Copy B node addr for rotation completion code
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.175.41.1 E:AVL.__BALNC:MV|AVL.REMOVE:AVL.__BALNC:MV 000590 13870600 ADDI A4, 0[A3]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00068713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 13
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.175.42 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC GOTO Asm000130 // Execute rotation completion code
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.175.42.1 AVL.__BALNC:GOTO|AVL.REMOVE:AVL.__BALNC:GOTO 000594 6F00C01D JAL 0, Asm000130 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 1DC0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +0001DC [HEX]
Immediate Sect. Offset.... 00000770 [HEX]
Immediate Encoded......... 0_00000000_0_0011101110 [BIN] Bits [20:1]
[+][-] 81.175.43 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.43.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000598 Asm000136 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.43.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000598 Asm000137 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.43.3 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.44 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.44 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.45 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC // LR Rotation - Top node is A, left child is B, its right child is C
81.175.46 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.48 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000598 03B88700 LD A6, 8+0[A5] // Get parent field from C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0087B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 15
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
81.175.49 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
[+][-] 81.175.50 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__EXTBL A6, A6 // Get balance of C node
Macro [AVL.__EXTBL] source location is [JAR: /arch/RISCV/macros/Avl.__extbl.mac]
81.175.50.1 ALNC:AVL.__EXTBL|AVL.REMOVE:AVL.__BALNC:AVL.__EXTBL 00059C 13783800 ANDI A6, 0b011[A6] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00387813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.50.2 ALNC:AVL.__EXTBL|AVL.REMOVE:AVL.__BALNC:AVL.__EXTBL 0005A0 1308F8FF ADDI A6, -1 // Subtract 1 to make it any of -1, 0, 1
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF80813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
81.175.51 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
[+][-] 81.175.52 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( A6 == 0 ), THEN // Check if C node balance is even
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.52.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( A6 == 0 ), true, Asm000147, Asm000145, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.52.1.81.175.52.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0005A4 63180800 BNE A6, 0, Asm000145
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00081863 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 000005B4 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
81.175.52.1.81.175.52.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0005A8 Asm000147 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.52.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.175.53 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T0, A5,, EVEN, LEFT, NOCLEAR, 8+0 // Set B node parent even/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.53.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0005A8 93E25700 ORI T0, 5[A5] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0057E293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 15
Immediate................. +005 [HEX]
Immediate Encoded......... 000000000101 [BIN] Bits [11:0]
[+][-] 81.175.54 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T1, A5,, EVEN, RIGHT, NOCLEAR, 8+0 // Set A node parent even/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.54.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0005AC 13E31700 ORI T1, 1[A5] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0017E313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 15
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 81.175.55 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ELSEIF ( A6 > 0 ) // Check if C node balance is high on left
Macro [ELSEIF] source location is [JAR: /arch/RISCV/macros/ElseIf.mac]
81.175.55.1 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.55.2 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF 0005B0 6F00C001 JAL Asm000146
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 01C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00001C [HEX]
Immediate Sect. Offset.... 000005CC [HEX]
Immediate Encoded......... 0_00000000_0_0000001110 [BIN] Bits [20:1]
81.175.55.3 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF 0005B4 Asm000145 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 81.175.55.4 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF __CondGen ( A6 > 0 ), true, Asm000149, Asm000148, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 81.175.55.4.81.175.55.4.1 ELSEIF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:ELSEIF:__CONDGEN BLE A6, 0, Asm000148
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
81.175.55.4.81.175.55.4.1.1 IF:__CONDGEN:BLE|AVL.REMOVE:AVL.__BALNC:ELSEIF:__CONDGEN:BLE 0005B4 63580001 BGE 0, A6, Asm000148
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 01005863 [BIG ENDIAN]
Source 1 Register...... 0
Source 2 Register...... 16
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 000005C4 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
81.175.55.4.81.175.55.4.2 ELSEIF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:ELSEIF:__CONDGEN 0005B8 Asm000149 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.55.5 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.175.56 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T0, A5,, EVEN, LEFT, NOCLEAR, 8+0 // Set B node parent even/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.56.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0005B8 93E25700 ORI T0, 5[A5] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0057E293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 15
Immediate................. +005 [HEX]
Immediate Encoded......... 000000000101 [BIN] Bits [11:0]
[+][-] 81.175.57 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T1, A5,, MINUS, RIGHT, NOCLEAR, 8+0 // Set A node parent minus/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
[+][-] 81.175.57.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA MV T1, A5 // Copy parent field - Set balance and link bits
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.175.57.1.81.175.57.1.1 C:AVL.__SETPA:MV|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA:MV 0005BC 13830700 ADDI T1, 0[A5]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00078313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.175.58 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ELSE // Balance is high on right
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
81.175.58.1 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.58.2 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE 0005C0 6F00C000 JAL Asm000146
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 00C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00000C [HEX]
Immediate Sect. Offset.... 000005CC [HEX]
Immediate Encoded......... 0_00000000_0_0000000110 [BIN] Bits [20:1]
81.175.58.3 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE 0005C4 Asm000148 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.58.4 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.175.59 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T0, A5,, PLUS, LEFT, NOCLEAR, 8+0 // Set B node parent plus/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.59.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0005C4 93E26700 ORI T0, 6[A5] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0067E293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 15
Immediate................. +006 [HEX]
Immediate Encoded......... 000000000110 [BIN] Bits [11:0]
[+][-] 81.175.60 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T1, A5,, EVEN, RIGHT, NOCLEAR, 8+0 // Set A node parent even/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.60.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0005C8 13E31700 ORI T1, 1[A5] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0017E313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 15
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 81.175.61 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.61.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 0005CC Asm000146 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.61.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.62 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.63 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0005CC 23B45600 SD T0, 8+0[A3] // Store B node parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0056B423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 13
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
81.175.64 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0005D0 23346700 SD T1, 8+0[A4] // Store A node parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00673423 [BIG ENDIAN]
Source 2 Register...... 6
Src. 1/Base Register...... 14
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
81.175.65 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.66 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0005D4 03B80700 LD A6, 0[A5] // Get left child of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0007B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
81.175.67 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0005D8 23B80601 SD A6, 16+0[A3] // Store it as right child of B node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0106B823 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 13
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 81.175.68 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( A6 != 0 ), THEN // Check if C node left child exists
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.68.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( A6 != 0 ), true, Asm000152, Asm000150, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.68.1.81.175.68.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0005DC 630A0800 BEQ A6, 0, Asm000150
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00080A63 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 000005F0 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
81.175.68.1.81.175.68.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0005E0 Asm000152 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.68.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.69 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0005E0 83328800 LD T0, 8+0[A6] // Get C node left child parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00883283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 16
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.175.70 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A6, T0, T0, A3,, RIGHT, CLEAR, 8+0 // Set C node child parent to B node - right link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.70.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0005E4 93F23200 ANDI T0, 3[T0] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0032F293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.70.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0005E8 B3E2D200 OR T0, A3 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00D2E2B3 [BIG ENDIAN]
Destination Register...... 5
Source 2 Register...... 13
Source 1 Register...... 5
81.175.70.3 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0005EC 23345800 SD T0, 8+0[A6] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00583423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 16
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.71 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.71.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 0005F0 Asm000150 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.71.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 0005F0 Asm000151 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.71.3 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.72 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.73 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0005F0 03B80701 LD A6, 16+0[A5] // get right child of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0107B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 15
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
81.175.74 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0005F4 23300701 SD A6, 0[A4] // Store it as left child of A node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01073023 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 14
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.175.75 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( A6 != 0 ), THEN // Check if node exists
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.75.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( A6 != 0 ), true, Asm000155, Asm000153, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.75.1.81.175.75.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0005F8 630C0800 BEQ A6, 0, Asm000153
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00080C63 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 018 [HEX]
Immediate Sect. Offset.... 00000610 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1100 [BIN] bits [12:1]
81.175.75.1.81.175.75.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0005FC Asm000155 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.75.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.76 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0005FC 83328800 LD T0, 8+0[A6] // Get C node right child parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00883283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 16
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.175.77 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A6, T0, T0, A4,, LEFT, CLEAR, 8+0 // Set C node child parent to B node - right link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.77.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000600 93F23200 ANDI T0, 3[T0] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0032F293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.77.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000604 93E24200 ORI T0, 4[T0] // Set link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0042E293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
81.175.77.3 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000608 B3E2E200 OR T0, A4 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00E2E2B3 [BIG ENDIAN]
Destination Register...... 5
Source 2 Register...... 14
Source 1 Register...... 5
81.175.77.4 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 00060C 23345800 SD T0, 8+0[A6] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00583423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 16
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.78 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.78.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000610 Asm000153 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.78.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000610 Asm000154 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.78.3 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.79 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000610 23B0D700 SD A3, 0[A5] // Set B node as left child of C node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00D7B023 [BIG ENDIAN]
Source 2 Register...... 13
Src. 1/Base Register...... 15
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
81.175.80 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000614 23B8E700 SD A4, 16+0[A5] // Set A node as right child of C node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00E7B823 [BIG ENDIAN]
Source 2 Register...... 14
Src. 1/Base Register...... 15
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
81.175.81 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
[+][-] 81.175.82 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A5, A2, A2,, EVEN,, CLEAR, 8+0 // Store A node parent in C node parnent field - even balance
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.82.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000618 1376C6FF ANDI A2, -4[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC67613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
81.175.82.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 00061C 13661600 ORI A2, 1[A2] // Set balance bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00166613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
81.175.82.3 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000620 23B4C700 SD A2, 8+0[A5] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C7B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 15
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.83 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC MV A4, A5 // Copy C node addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.175.83.1 E:AVL.__BALNC:MV|AVL.REMOVE:AVL.__BALNC:MV 000624 13870700 ADDI A4, 0[A5]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00078713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.175.84 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC GOTO Asm000130 // Execute rotation completion code
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.175.84.1 AVL.__BALNC:GOTO|AVL.REMOVE:AVL.__BALNC:GOTO 000628 6F008014 JAL 0, Asm000130 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 1480006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000148 [HEX]
Immediate Sect. Offset.... 00000770 [HEX]
Immediate Encoded......... 0_00000000_0_0010100100 [BIN] Bits [20:1]
81.175.85 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.85 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.86 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC // Check if right rotation
81.175.87 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
[+][-] 81.175.89 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ELSEIF ( T2 < A6 ), Precode= [!"LI A6, -1"]
Macro [ELSEIF] source location is [JAR: /arch/RISCV/macros/ElseIf.mac]
81.175.89.1 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.89.2 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF 00062C 6F00C010 JAL Asm000134
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 10C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00010C [HEX]
Immediate Sect. Offset.... 00000738 [HEX]
Immediate Encoded......... 0_00000000_0_0010000110 [BIN] Bits [20:1]
81.175.89.3 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF 000630 Asm000133 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 81.175.89.4 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF LI A6, -1
Macro [LI] source location is [JAR: /arch/RISCV/macros/Li.mac]
81.175.89.4.81.175.89.4.1 _BALNC:ELSEIF:LI|AVL.REMOVE:AVL.__BALNC:ELSEIF:LI 000630 1308F0FF ADDI A6, -1[0] // Load immediate value
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF00813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 0
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
[+][-] 81.175.89.5 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF __CondGen ( T2 < A6 ), true, Asm000157, Asm000156, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.89.5.81.175.89.5.1 ELSEIF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:ELSEIF:__CONDGEN 000634 63D20311 BGE T2, A6, Asm000156
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 1103D263 [BIG ENDIAN]
Source 1 Register...... 7
Source 2 Register...... 16
Immediate PCRel........... 104 [HEX]
Immediate Sect. Offset.... 00000738 [HEX]
Immediate Bits [12:1]..... 0_0_001000_0010 [BIN] bits [12:1]
81.175.89.5.81.175.89.5.2 ELSEIF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:ELSEIF:__CONDGEN 000638 Asm000157 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.89.6 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.89 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC // Handle right substree too high
81.175.91 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000638 83360701 LD A3, 16+0[A4] // Load B node addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 01073683 [BIG ENDIAN]
Destination Register...... 13
Source 1 Register...... 14
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
81.175.92 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 00063C 83B70600 LD A5, 0[A3] // Get C node addr
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0006B783 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 13
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
81.175.93 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000640 83B38600 LD T2, 8+0[A3] // get B node parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0086B383 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 13
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.175.94 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__EXTBL T2, T2 // Get B node balance
Macro [AVL.__EXTBL] source location is [JAR: /arch/RISCV/macros/Avl.__extbl.mac]
81.175.94.1 ALNC:AVL.__EXTBL|AVL.REMOVE:AVL.__BALNC:AVL.__EXTBL 000644 93F33300 ANDI T2, 0b011[T2] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0033F393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 7
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.94.2 ALNC:AVL.__EXTBL|AVL.REMOVE:AVL.__BALNC:AVL.__EXTBL 000648 9383F3FF ADDI T2, -1 // Subtract 1 to make it any of -1, 0, 1
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF38393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 7
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
81.175.95 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.95 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.96 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC // RR Rotation - Top node is A, left child is B, its right child is C if it exists
81.175.97 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
[+][-] 81.175.99 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( T2 <= 0 ), THEN // Check if RR rotation
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.99.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( T2 <= 0 ), true, Asm000160, Asm000158, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 81.175.99.1.81.175.99.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN BGT T2, 0, Asm000158
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
81.175.99.1.81.175.99.1.1.1 IF:__CONDGEN:BGT|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN:BGT 00064C 634C7004 BLT 0, T2, Asm000158
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 04704C63 [BIG ENDIAN]
Source 1 Register...... 0
Source 2 Register...... 7
Immediate PCRel........... 058 [HEX]
Immediate Sect. Offset.... 000006A4 [HEX]
Immediate Bits [12:1]..... 0_0_000010_1100 [BIN] bits [12:1]
81.175.99.1.81.175.99.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000650 Asm000160 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.99.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.100 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000650 2338F700 SD A5, 16+0[A4] // Make B node left child new right child A node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00F73823 [BIG ENDIAN]
Source 2 Register...... 15
Src. 1/Base Register...... 14
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 81.175.101 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( A5 != 0 ), THEN
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.101.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( A5 != 0 ), true, Asm000163, Asm000161, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.101.181.175.101.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000654 638A0700 BEQ A5, 0, Asm000161
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00078A63 [BIG ENDIAN]
Source 1 Register...... 15
Source 2 Register...... 0
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 00000668 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
81.175.101.181.175.101.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000658 Asm000163 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.101.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.102 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000658 03B88700 LD A6, 8+0[A5] // Get parent field of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0087B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 15
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.175.103 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A5, A6, A6, A4,, RIGHT, CLEAR, 8+0 // Set C node parent to A node - right link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.103.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 00065C 13783800 ANDI A6, 3[A6] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00387813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.103.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000660 3368E800 OR A6, A4 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00E86833 [BIG ENDIAN]
Destination Register...... 16
Source 2 Register...... 14
Source 1 Register...... 16
81.175.103.3 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000664 23B40701 SD A6, 8+0[A5] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0107B423 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 15
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.104 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.104.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000668 Asm000161 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.104.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000668 Asm000162 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.104.3 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 81.175.105 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( T2 != 0 ), THEN // Check if B node balance is not even
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.105.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( T2 != 0 ), true, Asm000166, Asm000164, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.105.181.175.105.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000668 638E0300 BEQ T2, 0, Asm000164
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00038E63 [BIG ENDIAN]
Source 1 Register...... 7
Source 2 Register...... 0
Immediate PCRel........... 01C [HEX]
Immediate Sect. Offset.... 00000684 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1110 [BIN] bits [12:1]
81.175.105.181.175.105.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 00066C Asm000166 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.105.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.175.106 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A4, A6, A3,, EVEN, LEFT, NOCLEAR, 8+0 // Set balance even - right link for A node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.106.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 00066C 13E85600 ORI A6, 5[A3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0056E813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 13
Immediate................. +005 [HEX]
Immediate Encoded......... 000000000101 [BIN] Bits [11:0]
81.175.106.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000670 23340701 SD A6, 8+0[A4] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01073423 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 14
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.107 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A3, A2, A2,, EVEN,, CLEAR, 8+0 // Set balance even - A node parent for B node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.107.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000674 1376C6FF ANDI A2, -4[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC67613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
81.175.107.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000678 13661600 ORI A2, 1[A2] // Set balance bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00166613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
81.175.107.3 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 00067C 23B4C600 SD A2, 8+0[A3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C6B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 13
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.108 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ELSE
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
81.175.108.1 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.108.2 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE 000680 6F008001 JAL Asm000165
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0180006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000018 [HEX]
Immediate Sect. Offset.... 00000698 [HEX]
Immediate Encoded......... 0_00000000_0_0000001100 [BIN] Bits [20:1]
81.175.108.3 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE 000684 Asm000164 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.108.4 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.175.109 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A4, A6, A3,, MINUS, LEFT, NOCLEAR, 8+0 // Set balance plus - right link for A node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.109.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000684 13E84600 ORI A6, 4[A3] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0046E813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 13
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
81.175.109.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000688 23340701 SD A6, 8+0[A4] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01073423 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 14
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.110 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A3, A2, A2,, PLUS,, CLEAR, 8+0 // Set balance minus for A node
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.110.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 00068C 1376C6FF ANDI A2, -4[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC67613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
81.175.110.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000690 13662600 ORI A2, 2[A2] // Set balance bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00266613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +002 [HEX]
Immediate Encoded......... 000000000010 [BIN] Bits [11:0]
81.175.110.3 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000694 23B4C600 SD A2, 8+0[A3] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C6B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 13
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.111 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.111.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000698 Asm000165 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.111.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.112 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000698 23B0E600 SD A4, 0[A3] // Set left child of B node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00E6B023 [BIG ENDIAN]
Source 2 Register...... 14
Src. 1/Base Register...... 13
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
81.175.113 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
[+][-] 81.175.114 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC MV A4, A3 // Copy B node addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.175.114.1 E:AVL.__BALNC:MV|AVL.REMOVE:AVL.__BALNC:MV 00069C 13870600 ADDI A4, 0[A3]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00068713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 13
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.175.115 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC GOTO Asm000130 // Execute rotation completion code
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.175.115.1 AVL.__BALNC:GOTO|AVL.REMOVE:AVL.__BALNC:GOTO 0006A0 6F00000D JAL 0, Asm000130 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0D00006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +0000D0 [HEX]
Immediate Sect. Offset.... 00000770 [HEX]
Immediate Encoded......... 0_00000000_0_0001101000 [BIN] Bits [20:1]
[+][-] 81.175.116 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.116.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 0006A4 Asm000158 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.116.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 0006A4 Asm000159 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.116.3 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.117 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.117 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.118 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC // RL Rotation - Top node is A, right child is B, its left child is C
81.175.119 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.121 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0006A4 03B88700 LD A6, 8+0[A5] // Get parent field from C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0087B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 15
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.175.122 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__EXTBL A6, A6 // Get balance of C node
Macro [AVL.__EXTBL] source location is [JAR: /arch/RISCV/macros/Avl.__extbl.mac]
81.175.122.1 ALNC:AVL.__EXTBL|AVL.REMOVE:AVL.__BALNC:AVL.__EXTBL 0006A8 13783800 ANDI A6, 0b011[A6] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00387813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.122.2 ALNC:AVL.__EXTBL|AVL.REMOVE:AVL.__BALNC:AVL.__EXTBL 0006AC 1308F8FF ADDI A6, -1 // Subtract 1 to make it any of -1, 0, 1
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFF80813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 16
Immediate................. -001 [HEX]
Immediate Encoded......... 111111111111 [BIN] Bits [11:0]
81.175.123 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
[+][-] 81.175.124 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( A6 == 0 ), THEN // Check if C node balance is even
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.124.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( A6 == 0 ), true, Asm000169, Asm000167, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.124.181.175.124.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0006B0 63180800 BNE A6, 0, Asm000167
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00081863 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 000006C0 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
81.175.124.181.175.124.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0006B4 Asm000169 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.124.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.175.125 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T0, A5,, EVEN, RIGHT, NOCLEAR, 8+0 // Set B node parent even/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.125.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0006B4 93E21700 ORI T0, 1[A5] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0017E293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 15
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 81.175.126 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T1, A5,, EVEN, LEFT, NOCLEAR, 8+0 // Set A node parent even/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.126.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0006B8 13E35700 ORI T1, 5[A5] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0057E313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 15
Immediate................. +005 [HEX]
Immediate Encoded......... 000000000101 [BIN] Bits [11:0]
[+][-] 81.175.127 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ELSEIF ( A6 < 0 ) // Check if C node balance is high on right
Macro [ELSEIF] source location is [JAR: /arch/RISCV/macros/ElseIf.mac]
81.175.127.1 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.127.2 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF 0006BC 6F00C001 JAL Asm000168
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 01C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00001C [HEX]
Immediate Sect. Offset.... 000006D8 [HEX]
Immediate Encoded......... 0_00000000_0_0000001110 [BIN] Bits [20:1]
81.175.127.3 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF 0006C0 Asm000167 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 81.175.127.4 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF __CondGen ( A6 < 0 ), true, Asm000171, Asm000170, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.127.481.175.127.4.1 ELSEIF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:ELSEIF:__CONDGEN 0006C0 63580800 BGE A6, 0, Asm000170
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 00085863 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 000006D0 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
81.175.127.481.175.127.4.2 ELSEIF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:ELSEIF:__CONDGEN 0006C4 Asm000171 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.127.5 L.__BALNC:ELSEIF|AVL.REMOVE:AVL.__BALNC:ELSEIF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.175.128 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T0, A5,, EVEN, RIGHT, NOCLEAR, 8+0 // Set B node parent even/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.128.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0006C4 93E21700 ORI T0, 1[A5] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0017E293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 15
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 81.175.129 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T1, A5,, PLUS, LEFT, NOCLEAR, 8+0 // Set A node parent plus/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.129.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0006C8 13E36700 ORI T1, 6[A5] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0067E313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 15
Immediate................. +006 [HEX]
Immediate Encoded......... 000000000110 [BIN] Bits [11:0]
[+][-] 81.175.130 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ELSE // Balance is high on left
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
81.175.130.1 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.130.2 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE 0006CC 6F00C000 JAL Asm000168
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 00C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00000C [HEX]
Immediate Sect. Offset.... 000006D8 [HEX]
Immediate Encoded......... 0_00000000_0_0000000110 [BIN] Bits [20:1]
81.175.130.3 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE 0006D0 Asm000170 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.130.4 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
[+][-] 81.175.131 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T0, A5,, MINUS, RIGHT, NOCLEAR, 8+0 // Set B node parent minus/right
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
[+][-] 81.175.131.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA MV T0, A5 // Copy parent field - Set balance and link bits
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.175.131.181.175.131.1.1 C:AVL.__SETPA:MV|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA:MV 0006D0 93820700 ADDI T0, 0[A5]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00078293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.175.132 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA , T1, A5,, EVEN, LEFT, NOCLEAR, 8+0 // Set A node parent even/left
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.132.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0006D4 13E35700 ORI T1, 5[A5] // Set balance and link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0057E313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 15
Immediate................. +005 [HEX]
Immediate Encoded......... 000000000101 [BIN] Bits [11:0]
[+][-] 81.175.133 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.133.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 0006D8 Asm000168 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.133.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.134 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0006D8 23B45600 SD T0, 8+0[A3] // Store B node parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0056B423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 13
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
81.175.135 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0006DC 23346700 SD T1, 8+0[A4] // Store A node parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00673423 [BIG ENDIAN]
Source 2 Register...... 6
Src. 1/Base Register...... 14
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
81.175.136 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.137 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0006E0 03B80701 LD A6, 16+0[A5] // Get right child of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0107B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 15
Immediate................. +010 [HEX]
Immediate Encoded......... 000000010000 [BIN] Bits [11:0]
81.175.138 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0006E4 23B00601 SD A6, 0[A3] // Store it as left child of B node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 0106B023 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 13
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.175.139 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( A6 != 0 ), THEN // Check if node exists
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.139.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( A6 != 0 ), true, Asm000174, Asm000172, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.139.181.175.139.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0006E8 630C0800 BEQ A6, 0, Asm000172
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00080C63 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 018 [HEX]
Immediate Sect. Offset.... 00000700 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1100 [BIN] bits [12:1]
81.175.139.181.175.139.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0006EC Asm000174 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.139.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.140 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0006EC 83328800 LD T0, 8+0[A6] // Get its parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00883283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 16
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.175.141 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A6, T0, T0, A3,, LEFT, CLEAR, 8+0 // Set C node child parent to B node - left link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.141.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0006F0 93F23200 ANDI T0, 3[T0] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0032F293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.141.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0006F4 93E24200 ORI T0, 4[T0] // Set link bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0042E293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
81.175.141.3 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0006F8 B3E2D200 OR T0, A3 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00D2E2B3 [BIG ENDIAN]
Destination Register...... 5
Source 2 Register...... 13
Source 1 Register...... 5
81.175.141.4 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 0006FC 23345800 SD T0, 8+0[A6] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00583423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 16
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.142 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.142.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000700 Asm000172 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.142.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000700 Asm000173 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.142.3 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.143 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.144 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000700 03B80700 LD A6, 0[A5] // Get left child of C node
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0007B803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
81.175.145 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000704 23380701 SD A6, 16+0[A4] // Store it as right child of A node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 01073823 [BIG ENDIAN]
Source 2 Register...... 16
Src. 1/Base Register...... 14
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 81.175.146 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( A6 != 0 ), THEN // Check if node exists
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.146.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( A6 != 0 ), true, Asm000177, Asm000175, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.146.181.175.146.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000708 630A0800 BEQ A6, 0, Asm000175
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00080A63 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 0000071C [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
81.175.146.181.175.146.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 00070C Asm000177 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.146.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.147 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 00070C 83328800 LD T0, 8+0[A6] // Get its parent field
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00883283 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 16
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 81.175.148 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A6, T0, T0, A4,, RIGHT, CLEAR, 8+0 // Set C node child parent to B node - right link
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.148.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000710 93F23200 ANDI T0, 3[T0] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0032F293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.148.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000714 B3E2E200 OR T0, A4 // Insert new parent addr
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00E2E2B3 [BIG ENDIAN]
Destination Register...... 5
Source 2 Register...... 14
Source 1 Register...... 5
81.175.148.3 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000718 23345800 SD T0, 8+0[A6] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00583423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 16
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.149 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.149.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 00071C Asm000175 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.149.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 00071C Asm000176 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.149.3 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.150 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 00071C 23B8D700 SD A3, 16+0[A5] // Set B node as right child of C node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00D7B823 [BIG ENDIAN]
Source 2 Register...... 13
Src. 1/Base Register...... 15
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
81.175.151 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000720 23B0E700 SD A4, 0[A5] // Set A node as left child of C node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00E7B023 [BIG ENDIAN]
Source 2 Register...... 14
Src. 1/Base Register...... 15
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
81.175.152 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
[+][-] 81.175.153 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__SETPA A5, A2, A2,, EVEN,, CLEAR, 8+0 // Store A node parent in C node parnent field - even balance
Macro [AVL.__SETPA] source location is [JAR: /arch/RISCV/macros/Avl.__setpa.mac]
81.175.153.1 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000724 1376C6FF ANDI A2, -4[A2] // Clear bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC67613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
81.175.153.2 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 000728 13661600 ORI A2, 1[A2] // Set balance bits
ORI: OR sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00166613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
81.175.153.3 ALNC:AVL.__SETPA|AVL.REMOVE:AVL.__BALNC:AVL.__SETPA 00072C 23B4C700 SD A2, 8+0[A5] // Store result in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C7B423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 15
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.154 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC MV A4, A5 // Copy C node addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.175.154.1 E:AVL.__BALNC:MV|AVL.REMOVE:AVL.__BALNC:MV 000730 13870700 ADDI A4, 0[A5]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00078713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 81.175.155 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC GOTO Asm000130 // Execute rotation completion code
Macro [GOTO] source location is [JAR: /arch/RISCV/macros/Goto.mac]
81.175.155.1 AVL.__BALNC:GOTO|AVL.REMOVE:AVL.__BALNC:GOTO 000734 6F00C003 JAL 0, Asm000130 // Unconditional branch
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 03C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00003C [HEX]
Immediate Sect. Offset.... 00000770 [HEX]
Immediate Encoded......... 0_00000000_0_0000011110 [BIN] Bits [20:1]
[+][-] 81.175.156 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.156.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000738 Asm000156 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.156.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000738 Asm000134 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.156.3 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.157 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.158 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.159 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC // No rotation
81.175.160 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.161 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000738 93821300 ADDI T0, 1[T2] // Encode balance
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00138293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 7
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
81.175.162 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 00073C 93F23200 ANDI T0, 0b011 // Keep low bits
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0032F293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
[+][-] 81.175.163 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__EXTPA A6, A2 // Extract addr of next node up
Macro [AVL.__EXTPA] source location is [JAR: /arch/RISCV/macros/Avl.__extpa.mac]
81.175.163.1 ALNC:AVL.__EXTPA|AVL.REMOVE:AVL.__BALNC:AVL.__EXTPA 000740 137886FF ANDI A6, ~ 0b111[A2] // Extract parent node addr from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF867813 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 12
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
81.175.164 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
[+][-] 81.175.165 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( A6 == 0 ), THEN // Check if root node
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.165.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( A6 == 0 ), true, Asm000180, Asm000178, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.165.181.175.165.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000744 63180800 BNE A6, 0, Asm000178
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00081863 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 0
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 00000754 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
81.175.165.181.175.165.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000748 Asm000180 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.165.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.166 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000748 2330E500 SD A4, 0[A0] // Update header
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00E53023 [BIG ENDIAN]
Source 2 Register...... 14
Src. 1/Base Register...... 10
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
81.175.167 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 00074C 23345700 SD T0, 8+0[A4] // Store balance only in parent field
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00573423 [BIG ENDIAN]
Source 2 Register...... 5
Src. 1/Base Register...... 14
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.168 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC BREAK // Done
Macro [BREAK] source location is [JAR: /arch/RISCV/macros/Break.mac]
81.175.168.1 VL.__BALNC:BREAK|AVL.REMOVE:AVL.__BALNC:BREAK 000750 6F000006 JAL Asm000132
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0600006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000060 [HEX]
Immediate Sect. Offset.... 000007B0 [HEX]
Immediate Encoded......... 0_00000000_0_0000110000 [BIN] Bits [20:1]
[+][-] 81.175.169 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.169.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000754 Asm000178 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.169.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000754 Asm000179 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.169.3 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.170 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.171 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000754 1376C6FF ANDI A2, ~ 0b011 // Clear balance bits in parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FFC67613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. -004 [HEX]
Immediate Encoded......... 111111111100 [BIN] Bits [11:0]
81.175.172 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000758 33665600 OR A2, T0 // Insert new balance
OR: OR SReg1 with SReg2 and store result in RegD
Machine Instruction....... 00566633 [BIG ENDIAN]
Destination Register...... 12
Source 2 Register...... 5
Source 1 Register...... 12
81.175.173 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 00075C 2334C700 SD A2,8+0[A4] // Store parent field in node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C73423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 14
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.174 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC MV A4, A6 // Copy next node up addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.175.174.1 E:AVL.__BALNC:MV|AVL.REMOVE:AVL.__BALNC:MV 000760 13070800 ADDI A4, 0[A6]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00080713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 16
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
81.175.175 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000764 93F31300 ANDI T2, 0b001 // Extract low bit of balance
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 0013F393 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 7
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 81.175.176 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( T2 != 0 ), BREAK // Done if low bit is on (balance is +/- 1)
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.176.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( T2 != 0 ), false, Asm000132, Asm000181, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.176.181.175.176.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000768 63940304 BNE T2, 0, Asm000132
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 04039463 [BIG ENDIAN]
Source 1 Register...... 7
Source 2 Register...... 0
Immediate PCRel........... 048 [HEX]
Immediate Sect. Offset.... 000007B0 [HEX]
Immediate Bits [12:1]..... 0_0_000010_0100 [BIN] bits [12:1]
81.175.176.181.175.176.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 00076C Asm000181 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 81.175.177 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC CONTINUE // Continue otherwise
Macro [CONTINUE] source location is [JAR: /arch/RISCV/macros/Continue.mac]
81.175.177.1 __BALNC:CONTINUE|AVL.REMOVE:AVL.__BALNC:CONTINUE 00076C 6FF0DFD9 JAL Asm000131
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... D9DFF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -000264 [HEX]
Immediate Sect. Offset.... 00000508 [HEX]
Immediate Encoded......... 1_11111111_1_1011001110 [BIN] Bits [20:1]
81.175.178 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.178 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
81.175.179 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC // Rotation completion common code
81.175.180 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC //
[+][-] 81.175.182 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC Asm000130 AVL.__EXTPA T0, A2 // Get A node parent addr
Macro [AVL.__EXTPA] source location is [JAR: /arch/RISCV/macros/Avl.__extpa.mac]
81.175.182.1 ALNC:AVL.__EXTPA|AVL.REMOVE:AVL.__BALNC:AVL.__EXTPA 000770 937286FF Asm000130 ANDI T0, ~ 0b111[A2] // Extract parent node addr from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF867293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 12
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 81.175.183 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( T0 == 0 ), THEN // Check if root node
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.183.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( T0 == 0 ), true, Asm000184, Asm000182, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.183.181.175.183.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000774 639A0200 BNE T0, 0, Asm000182
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... 00029A63 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 0
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 00000788 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
81.175.183.181.175.183.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000778 Asm000184 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.183.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.184 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000778 2330E500 SD A4, 0[A0] // Update header
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00E53023 [BIG ENDIAN]
Source 2 Register...... 14
Src. 1/Base Register...... 10
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.175.185 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__EXTBB A2, A2 // Keep only balance bits
Macro [AVL.__EXTBB] source location is [JAR: /arch/RISCV/macros/Avl.__extbb.mac]
81.175.185.1 ALNC:AVL.__EXTBB|AVL.REMOVE:AVL.__BALNC:AVL.__EXTBB 00077C 13763600 ANDI A2, 0b011[A2] // Extract balance bits from parent field
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00367613 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 12
Immediate................. +003 [HEX]
Immediate Encoded......... 000000000011 [BIN] Bits [11:0]
81.175.186 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000780 2334C700 SD A2, 8+0[A4] // Store it back
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C73423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 14
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.187 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC BREAK // Done - root node
Macro [BREAK] source location is [JAR: /arch/RISCV/macros/Break.mac]
81.175.187.1 VL.__BALNC:BREAK|AVL.REMOVE:AVL.__BALNC:BREAK 000784 6F00C002 JAL Asm000132
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 02C0006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +00002C [HEX]
Immediate Sect. Offset.... 000007B0 [HEX]
Immediate Encoded......... 0_00000000_0_0000010110 [BIN] Bits [20:1]
[+][-] 81.175.188 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.188.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000788 Asm000182 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.188.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 000788 Asm000183 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.188.3 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.189 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC
81.175.190 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000788 2334C700 SD A2,8+0[A4] // Store parent field in node
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C73423 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 14
Immediate Displacement.... +008 [HEX]
Immediate Encoded......... 0000000_01000 [BIN] Bits [11:0]
[+][-] 81.175.191 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC AVL.__EXTLT T1, A2 // Get parent link type of A node
Macro [AVL.__EXTLT] source location is [JAR: /arch/RISCV/macros/Avl.__extlt.mac]
81.175.191.1 ALNC:AVL.__EXTLT|AVL.REMOVE:AVL.__BALNC:AVL.__EXTLT 00078C 13734600 ANDI T1, 0b100[A2] // Extract parent node link type
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00467313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 12
Immediate................. +004 [HEX]
Immediate Encoded......... 000000000100 [BIN] Bits [11:0]
[+][-] 81.175.192 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( T1 > 0 ), THEN // Check if left link
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.192.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( T1 > 0 ), true, Asm000187, Asm000185, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 81.175.192.181.175.192.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN BLE T1, 0, Asm000185
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
81.175.192.181.175.192.1.1.1 IF:__CONDGEN:BLE|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN:BLE 000790 63566000 BGE 0, T1, Asm000185
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 00605663 [BIG ENDIAN]
Source 1 Register...... 0
Source 2 Register...... 6
Immediate PCRel........... 00C [HEX]
Immediate Sect. Offset.... 0000079C [HEX]
Immediate Bits [12:1]..... 0_0_000000_0110 [BIN] bits [12:1]
81.175.192.181.175.192.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 000794 Asm000187 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.192.2 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.193 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 000794 23B0E200 SD A4, 0[T0] // Set new top node as left child of parent
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00E2B023 [BIG ENDIAN]
Source 2 Register...... 14
Src. 1/Base Register...... 5
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 81.175.194 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ELSE
Macro [ELSE] source location is [JAR: /arch/RISCV/macros/Else.mac]
81.175.194.1 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
81.175.194.2 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE 000798 6F008000 JAL Asm000186
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... 0080006F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... +000008 [HEX]
Immediate Sect. Offset.... 000007A0 [HEX]
Immediate Encoded......... 0_00000000_0_0000000100 [BIN] Bits [20:1]
81.175.194.3 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE 00079C Asm000185 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.194.4 AVL.__BALNC:ELSE|AVL.REMOVE:AVL.__BALNC:ELSE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
81.175.195 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 00079C 23B8E200 SD A4, 16+0[T0] // Set new top node as right child of parent
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00E2B823 [BIG ENDIAN]
Source 2 Register...... 14
Src. 1/Base Register...... 5
Immediate Displacement.... +010 [HEX]
Immediate Encoded......... 0000000_10000 [BIN] Bits [11:0]
[+][-] 81.175.196 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDIF
Macro [ENDIF] source location is [JAR: /arch/RISCV/macros/EndIf.mac]
81.175.196.1 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF 0007A0 Asm000186 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.196.2 VL.__BALNC:ENDIF|AVL.REMOVE:AVL.__BALNC:ENDIF INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 81.175.197 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC MV A4, T0 // Get addr of parent node
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
81.175.197.1 E:AVL.__BALNC:MV|AVL.REMOVE:AVL.__BALNC:MV 0007A0 13870200 ADDI A4, 0[T0]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00028713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 5
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
81.175.198 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC 0007A4 93721600 ANDI T0, 0b001[A2] // Extract low bit of balance
ANDI: AND sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00167293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 12
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 81.175.199 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC IF ( T0 != 0 && A4 != 0 ), CONTINUE // Done if low bit is on (balance is zero) or not root node
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 81.175.199.1 E:AVL.__BALNC:IF|AVL.REMOVE:AVL.__BALNC:IF __CondGen ( T0 != 0 && A4 != 0 ), false, Asm000131, Asm000188, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
81.175.199.181.175.199.1.1 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0007A8 63840200 BEQ T0, 0, Asm000188
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00028463 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 0
Immediate PCRel........... 008 [HEX]
Immediate Sect. Offset.... 000007B0 [HEX]
Immediate Bits [12:1]..... 0_0_000000_0100 [BIN] bits [12:1]
81.175.199.181.175.199.1.2 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0007AC E31E07D4 BNE A4, 0, Asm000131
BNE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 != Reg2 (signed)
Machine Instruction....... D4071EE3 [BIG ENDIAN]
Source 1 Register...... 14
Source 2 Register...... 0
Immediate PCRel........... -2A4 [HEX]
Immediate Sect. Offset.... 00000508 [HEX]
Immediate Bits [12:1]..... 1_1_101010_1110 [BIN] bits [12:1]
81.175.199.181.175.199.1.3 LNC:IF:__CONDGEN|AVL.REMOVE:AVL.__BALNC:IF:__CONDGEN 0007B0 Asm000188 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 81.175.200 MOVE:AVL.__BALNC|AVL.REMOVE:AVL.__BALNC ENDDO // ENd of balance block
Macro [ENDDO] source location is [JAR: /arch/RISCV/macros/Enddo.mac]
81.175.200.1 VL.__BALNC:ENDDO|AVL.REMOVE:AVL.__BALNC:ENDDO 0007B0 Asm000132 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.175.200.2 VL.__BALNC:ENDDO|AVL.REMOVE:AVL.__BALNC:ENDDO INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 81.176 |AVL.REMOVE ENDDO
Macro [ENDDO] source location is [JAR: /arch/RISCV/macros/Enddo.mac]
81.176.1 AVL.REMOVE:ENDDO|AVL.REMOVE:ENDDO 0007B0 Asm000069 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
81.176.2 AVL.REMOVE:ENDDO|AVL.REMOVE:ENDDO INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 82 | EXIT // Return to caller
Macro [EXIT] source location is [JAR: /arch/RISCV/macros/Exit.mac]
82.1 |EXIT 0007B0 67800000 JALR 0, 0[ra] // Return to caller
JALR: Jump to ( Reg1 + immediate ) address, and store link address in RegD
Machine Instruction....... 00008067 [BIG ENDIAN]
Destination Register...... 0
Source 1 Register...... 1
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
83 | //
84 | END
Code SECTION 00008 000007B4 .text PROGBITS ALLOC+EXECUTE
[+][-] A0 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 61.84
Referenced in Statement: 70.1
Referenced in Statement: 70.25.156
Referenced in Statement: 70.25.173
Referenced in Statement: 70.6
Referenced in Statement: 74
Referenced in Statement: 81.138
Referenced in Statement: 81.14
Referenced in Statement: 81.175.166
Referenced in Statement: 81.175.184
Referenced in Statement: 81.34
Referenced in Statement: 81.58
Referenced in Statement: 81.92
[+][-] A1 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 61.85
Referenced in Statement: 70.10.1
Referenced in Statement: 70.13
Referenced in Statement: 70.18
Referenced in Statement: 70.22
Referenced in Statement: 70.23
Referenced in Statement: 70.24
Referenced in Statement: 70.3
Referenced in Statement: 70.4.2
Referenced in Statement: 70.5
Referenced in Statement: 70.6
Referenced in Statement: 81.2
Referenced in Statement: 81.3
Referenced in Statement: 81.6
[+][-] A2 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 61.86
Referenced in Statement: 70.25.11.1
Referenced in Statement: 70.25.11.2
Referenced in Statement: 70.25.12
Referenced in Statement: 70.25.151
Referenced in Statement: 70.25.165.1.1
Referenced in Statement: 70.25.18.1.1.1
Referenced in Statement: 70.25.21
Referenced in Statement: 70.25.22.1
Referenced in Statement: 70.25.22.2
Referenced in Statement: 70.25.27.1.1
Referenced in Statement: 70.25.84.5.1
Referenced in Statement: 70.25.88
Referenced in Statement: 70.25.89.1
Referenced in Statement: 70.25.89.2
Referenced in Statement: 70.25.94.1.1.1
Referenced in Statement: 81.103
Referenced in Statement: 81.114.1.1
Referenced in Statement: 81.116
Referenced in Statement: 81.117.1
Referenced in Statement: 81.117.2
Referenced in Statement: 81.117.3
Referenced in Statement: 81.121.1
Referenced in Statement: 81.123
Referenced in Statement: 81.149
Referenced in Statement: 81.161.1
Referenced in Statement: 81.163
Referenced in Statement: 81.164.1
Referenced in Statement: 81.164.2
Referenced in Statement: 81.164.3
Referenced in Statement: 81.164.4
Referenced in Statement: 81.168.1.1
Referenced in Statement: 81.170
Referenced in Statement: 81.175.10
Referenced in Statement: 81.175.107.1
Referenced in Statement: 81.175.107.2
Referenced in Statement: 81.175.107.3
Referenced in Statement: 81.175.11.1
Referenced in Statement: 81.175.110.1
Referenced in Statement: 81.175.110.2
Referenced in Statement: 81.175.110.3
Referenced in Statement: 81.175.153.1
Referenced in Statement: 81.175.153.2
Referenced in Statement: 81.175.153.3
Referenced in Statement: 81.175.163.1
Referenced in Statement: 81.175.171
Referenced in Statement: 81.175.172
Referenced in Statement: 81.175.173
Referenced in Statement: 81.175.182.1
Referenced in Statement: 81.175.185.1
Referenced in Statement: 81.175.186
Referenced in Statement: 81.175.190
Referenced in Statement: 81.175.191.1
Referenced in Statement: 81.175.198
Referenced in Statement: 81.175.35.1
Referenced in Statement: 81.175.35.2
Referenced in Statement: 81.175.35.3
Referenced in Statement: 81.175.38.1
Referenced in Statement: 81.175.38.2
Referenced in Statement: 81.175.4.1
Referenced in Statement: 81.175.7.1
Referenced in Statement: 81.175.82.1
Referenced in Statement: 81.175.82.2
Referenced in Statement: 81.175.82.3
Referenced in Statement: 81.3
Referenced in Statement: 81.31
Referenced in Statement: 81.35.1
Referenced in Statement: 81.36
Referenced in Statement: 81.4.1
Referenced in Statement: 81.42.1
Referenced in Statement: 81.42.2
Referenced in Statement: 81.42.3
Referenced in Statement: 81.47.1
Referenced in Statement: 81.47.2
Referenced in Statement: 81.47.3
Referenced in Statement: 81.47.4
Referenced in Statement: 81.5.1
Referenced in Statement: 81.55
Referenced in Statement: 81.59.1
Referenced in Statement: 81.60
Referenced in Statement: 81.66.1
Referenced in Statement: 81.66.2
Referenced in Statement: 81.66.3
Referenced in Statement: 81.66.4
Referenced in Statement: 81.71.1
Referenced in Statement: 81.71.2
Referenced in Statement: 81.71.3
Referenced in Statement: 81.78.1
[+][-] A3 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 61.87
Referenced in Statement: 81.108.1.1
Referenced in Statement: 81.109
Referenced in Statement: 81.11.1.1
Referenced in Statement: 81.110
Referenced in Statement: 81.111.3
Referenced in Statement: 81.150
Referenced in Statement: 81.151
Referenced in Statement: 81.152.3
Referenced in Statement: 81.175.106.1
Referenced in Statement: 81.175.107.3
Referenced in Statement: 81.175.109.1
Referenced in Statement: 81.175.110.3
Referenced in Statement: 81.175.112
Referenced in Statement: 81.175.114.1
Referenced in Statement: 81.175.134
Referenced in Statement: 81.175.138
Referenced in Statement: 81.175.141.3
Referenced in Statement: 81.175.150
Referenced in Statement: 81.175.19
Referenced in Statement: 81.175.20
Referenced in Statement: 81.175.21
Referenced in Statement: 81.175.34.1
Referenced in Statement: 81.175.35.3
Referenced in Statement: 81.175.37.1
Referenced in Statement: 81.175.38.2
Referenced in Statement: 81.175.40
Referenced in Statement: 81.175.41.1
Referenced in Statement: 81.175.63
Referenced in Statement: 81.175.67
Referenced in Statement: 81.175.70.2
Referenced in Statement: 81.175.79
Referenced in Statement: 81.175.91
Referenced in Statement: 81.175.92
Referenced in Statement: 81.175.93
Referenced in Statement: 81.2
Referenced in Statement: 81.30.1.1
Referenced in Statement: 81.55
Referenced in Statement: 81.58
Referenced in Statement: 81.60
Referenced in Statement: 81.65
Referenced in Statement: 81.66.4
Referenced in Statement: 81.70
Referenced in Statement: 81.71.3
Referenced in Statement: 81.84.1
[+][-] A4 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 61.88
Referenced in Statement: 81.112.1
Referenced in Statement: 81.113
Referenced in Statement: 81.114.1.1
Referenced in Statement: 81.117.2
Referenced in Statement: 81.13.1.1
Referenced in Statement: 81.137.1.1
Referenced in Statement: 81.141
Referenced in Statement: 81.143
Referenced in Statement: 81.158.1
Referenced in Statement: 81.160
Referenced in Statement: 81.161.1
Referenced in Statement: 81.164.3
Referenced in Statement: 81.175.10
Referenced in Statement: 81.175.100
Referenced in Statement: 81.175.103.2
Referenced in Statement: 81.175.106.2
Referenced in Statement: 81.175.109.2
Referenced in Statement: 81.175.112
Referenced in Statement: 81.175.114.1
Referenced in Statement: 81.175.135
Referenced in Statement: 81.175.145
Referenced in Statement: 81.175.148.2
Referenced in Statement: 81.175.151
Referenced in Statement: 81.175.154.1
Referenced in Statement: 81.175.166
Referenced in Statement: 81.175.167
Referenced in Statement: 81.175.173
Referenced in Statement: 81.175.174.1
Referenced in Statement: 81.175.184
Referenced in Statement: 81.175.186
Referenced in Statement: 81.175.19
Referenced in Statement: 81.175.190
Referenced in Statement: 81.175.193
Referenced in Statement: 81.175.195
Referenced in Statement: 81.175.197.1
Referenced in Statement: 81.175.199.1.2
Referenced in Statement: 81.175.28
Referenced in Statement: 81.175.31.3
Referenced in Statement: 81.175.34.2
Referenced in Statement: 81.175.37.2
Referenced in Statement: 81.175.4.1
Referenced in Statement: 81.175.40
Referenced in Statement: 81.175.41.1
Referenced in Statement: 81.175.64
Referenced in Statement: 81.175.74
Referenced in Statement: 81.175.77.3
Referenced in Statement: 81.175.80
Referenced in Statement: 81.175.83.1
Referenced in Statement: 81.175.91
Referenced in Statement: 81.19
Referenced in Statement: 81.23
Referenced in Statement: 81.33.1.1
Referenced in Statement: 81.4.1
Referenced in Statement: 81.41
Referenced in Statement: 81.42.2
Referenced in Statement: 81.46
Referenced in Statement: 81.47.3
Referenced in Statement: 81.57.1.1
Referenced in Statement: 81.65
Referenced in Statement: 81.66.3
Referenced in Statement: 81.70
Referenced in Statement: 81.71.2
Referenced in Statement: 81.91.1.1
Referenced in Statement: 81.95
Referenced in Statement: 81.97
[+][-] A5 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 61.89
Referenced in Statement: 81.104
Referenced in Statement: 81.105
Referenced in Statement: 81.106.3
Referenced in Statement: 81.11.1.2
Referenced in Statement: 81.130.1
Referenced in Statement: 81.154.1.1
Referenced in Statement: 81.155
Referenced in Statement: 81.156
Referenced in Statement: 81.157.3
Referenced in Statement: 81.175.100
Referenced in Statement: 81.175.101.1.1
Referenced in Statement: 81.175.102
Referenced in Statement: 81.175.103.3
Referenced in Statement: 81.175.121
Referenced in Statement: 81.175.125.1
Referenced in Statement: 81.175.126.1
Referenced in Statement: 81.175.128.1
Referenced in Statement: 81.175.129.1
Referenced in Statement: 81.175.131.1.1
Referenced in Statement: 81.175.132.1
Referenced in Statement: 81.175.137
Referenced in Statement: 81.175.144
Referenced in Statement: 81.175.150
Referenced in Statement: 81.175.151
Referenced in Statement: 81.175.153.3
Referenced in Statement: 81.175.154.1
Referenced in Statement: 81.175.20
Referenced in Statement: 81.175.28
Referenced in Statement: 81.175.29.1.1
Referenced in Statement: 81.175.30
Referenced in Statement: 81.175.31.4
Referenced in Statement: 81.175.48
Referenced in Statement: 81.175.53.1
Referenced in Statement: 81.175.54.1
Referenced in Statement: 81.175.56.1
Referenced in Statement: 81.175.57.1.1
Referenced in Statement: 81.175.59.1
Referenced in Statement: 81.175.60.1
Referenced in Statement: 81.175.66
Referenced in Statement: 81.175.73
Referenced in Statement: 81.175.79
Referenced in Statement: 81.175.80
Referenced in Statement: 81.175.82.3
Referenced in Statement: 81.175.83.1
Referenced in Statement: 81.175.92
Referenced in Statement: 81.31
Referenced in Statement: 81.34
Referenced in Statement: 81.36
Referenced in Statement: 81.41
Referenced in Statement: 81.42.3
Referenced in Statement: 81.46
Referenced in Statement: 81.47.4
Referenced in Statement: 81.54.1.1
Referenced in Statement: 81.6
[+][-] A6 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 61.90
Referenced in Statement: 81.105
Referenced in Statement: 81.106.1
Referenced in Statement: 81.106.2
Referenced in Statement: 81.106.3
Referenced in Statement: 81.110
Referenced in Statement: 81.111.1
Referenced in Statement: 81.111.2
Referenced in Statement: 81.111.3
Referenced in Statement: 81.140.1.1
Referenced in Statement: 81.151
Referenced in Statement: 81.152.1
Referenced in Statement: 81.152.2
Referenced in Statement: 81.152.3
Referenced in Statement: 81.156
Referenced in Statement: 81.157.1
Referenced in Statement: 81.157.2
Referenced in Statement: 81.157.3
Referenced in Statement: 81.175.102
Referenced in Statement: 81.175.103.1
Referenced in Statement: 81.175.103.2
Referenced in Statement: 81.175.103.3
Referenced in Statement: 81.175.106.1
Referenced in Statement: 81.175.106.2
Referenced in Statement: 81.175.109.1
Referenced in Statement: 81.175.109.2
Referenced in Statement: 81.175.12
Referenced in Statement: 81.175.121
Referenced in Statement: 81.175.122.1
Referenced in Statement: 81.175.122.2
Referenced in Statement: 81.175.124.1.1
Referenced in Statement: 81.175.127.4.1
Referenced in Statement: 81.175.137
Referenced in Statement: 81.175.138
Referenced in Statement: 81.175.139.1.1
Referenced in Statement: 81.175.140
Referenced in Statement: 81.175.141.4
Referenced in Statement: 81.175.144
Referenced in Statement: 81.175.145
Referenced in Statement: 81.175.146.1.1
Referenced in Statement: 81.175.147
Referenced in Statement: 81.175.148.3
Referenced in Statement: 81.175.163.1
Referenced in Statement: 81.175.165.1.1
Referenced in Statement: 81.175.17.1
Referenced in Statement: 81.175.174.1
Referenced in Statement: 81.175.18.1.1.1
Referenced in Statement: 81.175.30
Referenced in Statement: 81.175.31.1
Referenced in Statement: 81.175.31.2
Referenced in Statement: 81.175.31.3
Referenced in Statement: 81.175.31.4
Referenced in Statement: 81.175.34.1
Referenced in Statement: 81.175.34.2
Referenced in Statement: 81.175.37.1
Referenced in Statement: 81.175.37.2
Referenced in Statement: 81.175.48
Referenced in Statement: 81.175.50.1
Referenced in Statement: 81.175.50.2
Referenced in Statement: 81.175.52.1.1
Referenced in Statement: 81.175.55.4.1.1
Referenced in Statement: 81.175.66
Referenced in Statement: 81.175.67
Referenced in Statement: 81.175.68.1.1
Referenced in Statement: 81.175.69
Referenced in Statement: 81.175.7.1
Referenced in Statement: 81.175.70.3
Referenced in Statement: 81.175.73
Referenced in Statement: 81.175.74
Referenced in Statement: 81.175.75.1.1
Referenced in Statement: 81.175.76
Referenced in Statement: 81.175.77.4
Referenced in Statement: 81.175.8
Referenced in Statement: 81.175.89.4.1
Referenced in Statement: 81.175.89.5.1
Referenced in Statement: 81.175.9
Referenced in Statement: 81.18.1.1
Referenced in Statement: 81.40.1.1
Referenced in Statement: 81.5.1
Referenced in Statement: 81.64.1.1
Referenced in Statement: 81.94.1.1
[+][-] A7 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 61.91
[+][-] ASM000001 OFFSET [Code] 00002 00004 00001 000004 00000060
Defined in Statement: 70.16
Referenced in Statement: 70.10.6.1.1.1
[+][-] ASM000002 OFFSET [Code] 00001 00001 00000 000000 00000020
Defined in Statement: 70.7.3
Referenced in Statement: 70.2.1.1
[+][-] ASM000003 OFFSET [Code] 00001 00001 00000 000000 000002E0
Defined in Statement: 70.26.1
Referenced in Statement: 70.7.2
[+][-] ASM000004 OFFSET [Code] 00001 00001 00000 000000 00000008
Defined in Statement: 70.2.1.2
[+][-] ASM000005 OFFSET [Code] 00001 00001 00000 000000 00000020
Defined in Statement: 70.8.1
Referenced in Statement: 70.12.1.1
Referenced in Statement: 70.17.1.1
[+][-] ASM000006 OFFSET [Code] 00001 00001 00000 000000 00000070
Defined in Statement: 70.20.1
Referenced in Statement: 70.15.1
[+][-] ASM000007 OFFSET [Code] 00001 00001 00000 000000 0000002C
Defined in Statement: 70.10.3.1
[+][-] ASM000008 OFFSET [Code] 00001 00001 00000 000000 0000002C
Defined in Statement: 70.10.3.2
Referenced in Statement: 70.10.11.1
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Defined in Statement: 70.10.11.2
Referenced in Statement: 70.10.7.1.1
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Defined in Statement: 70.10.6.1.2
[+][-] ASM000011 OFFSET [Code] 00001 00001 00000 000000 0000003C
Defined in Statement: 70.10.7.1.2
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Defined in Statement: 70.10.8.1.2
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Defined in Statement: 70.12.1.2
[+][-] ASM000014 OFFSET [Code] 00001 00001 00000 000000 00000068
Defined in Statement: 70.17.1.2
[+][-] ASM000015 OFFSET [Code] 00002 00004 00001 000004 000002B0
Defined in Statement: 70.25.171.1
Referenced in Statement: 70.25.105.1
Referenced in Statement: 70.25.145.1
Referenced in Statement: 70.25.37.1
Referenced in Statement: 70.25.79.1
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Defined in Statement: 70.25.6.1
Referenced in Statement: 70.25.165.1.1
[+][-] ASM000017 OFFSET [Code] 00001 00001 00000 000000 000002E0
Defined in Statement: 70.25.186.1
Referenced in Statement: 70.25.158.1
Referenced in Statement: 70.25.166.1
Referenced in Statement: 70.25.176.1
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Defined in Statement: 70.25.84.3
Referenced in Statement: 70.25.18.1.1.1
[+][-] ASM000019 OFFSET [Code] 00001 00001 00000 000000 0000027C
Defined in Statement: 70.25.146.2
Referenced in Statement: 70.25.84.2
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Defined in Statement: 70.25.18.1.2
[+][-] ASM000021 OFFSET [Code] 00001 00001 00000 000000 000000F8
Defined in Statement: 70.25.38.1
Referenced in Statement: 70.25.27.1.1
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Defined in Statement: 70.25.38.2
[+][-] ASM000023 OFFSET [Code] 00001 00001 00000 000000 000000BC
Defined in Statement: 70.25.27.1.2
[+][-] ASM000024 OFFSET [Code] 00001 00001 00000 000000 000000D8
Defined in Statement: 70.25.32.1
Referenced in Statement: 70.25.29.1.1
[+][-] ASM000025 OFFSET [Code] 00001 00001 00000 000000 000000D8
Defined in Statement: 70.25.32.2
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Defined in Statement: 70.25.29.1.2
[+][-] ASM000027 OFFSET [Code] 00001 00001 00000 000000 00000114
Defined in Statement: 70.25.50.3
Referenced in Statement: 70.25.47.1.1
[+][-] ASM000028 OFFSET [Code] 00001 00001 00000 000000 0000012C
Defined in Statement: 70.25.56.1
Referenced in Statement: 70.25.50.2
Referenced in Statement: 70.25.53.2
[+][-] ASM000029 OFFSET [Code] 00001 00001 00000 000000 00000108
Defined in Statement: 70.25.47.1.2
[+][-] ASM000030 OFFSET [Code] 00001 00001 00000 000000 00000124
Defined in Statement: 70.25.53.3
Referenced in Statement: 70.25.50.4.1.1
[+][-] ASM000031 OFFSET [Code] 00001 00001 00000 000000 00000118
Defined in Statement: 70.25.50.4.2
[+][-] ASM000032 OFFSET [Code] 00001 00001 00000 000000 00000150
Defined in Statement: 70.25.66.1
Referenced in Statement: 70.25.63.1.1
[+][-] ASM000033 OFFSET [Code] 00001 00001 00000 000000 00000150
Defined in Statement: 70.25.66.2
[+][-] ASM000034 OFFSET [Code] 00001 00001 00000 000000 00000140
Defined in Statement: 70.25.63.1.2
[+][-] ASM000035 OFFSET [Code] 00001 00001 00000 000000 00000170
Defined in Statement: 70.25.73.1
Referenced in Statement: 70.25.70.1.1
[+][-] ASM000036 OFFSET [Code] 00001 00001 00000 000000 00000170
Defined in Statement: 70.25.73.2
[+][-] ASM000037 OFFSET [Code] 00001 00001 00000 000000 0000015C
Defined in Statement: 70.25.70.1.2
[+][-] ASM000038 OFFSET [Code] 00001 00001 00000 000000 0000027C
Defined in Statement: 70.25.146.1
Referenced in Statement: 70.25.84.5.1
[+][-] ASM000039 OFFSET [Code] 00001 00001 00000 000000 00000198
Defined in Statement: 70.25.84.5.2
[+][-] ASM000040 OFFSET [Code] 00001 00001 00000 000000 000001E8
Defined in Statement: 70.25.106.1
Referenced in Statement: 70.25.94.1.1.1
[+][-] ASM000041 OFFSET [Code] 00001 00001 00000 000000 000001E8
Defined in Statement: 70.25.106.2
[+][-] ASM000042 OFFSET [Code] 00001 00001 00000 000000 000001B0
Defined in Statement: 70.25.94.1.2
[+][-] ASM000043 OFFSET [Code] 00001 00001 00000 000000 000001C8
Defined in Statement: 70.25.99.1
Referenced in Statement: 70.25.96.1.1
[+][-] ASM000044 OFFSET [Code] 00001 00001 00000 000000 000001C8
Defined in Statement: 70.25.99.2
[+][-] ASM000045 OFFSET [Code] 00001 00001 00000 000000 000001B8
Defined in Statement: 70.25.96.1.2
[+][-] ASM000046 OFFSET [Code] 00001 00001 00000 000000 00000204
Defined in Statement: 70.25.117.3
Referenced in Statement: 70.25.114.1.1
[+][-] ASM000047 OFFSET [Code] 00001 00001 00000 000000 0000021C
Defined in Statement: 70.25.123.1
Referenced in Statement: 70.25.117.2
Referenced in Statement: 70.25.120.2
[+][-] ASM000048 OFFSET [Code] 00001 00001 00000 000000 000001F8
Defined in Statement: 70.25.114.1.2
[+][-] ASM000049 OFFSET [Code] 00001 00001 00000 000000 00000214
Defined in Statement: 70.25.120.3
Referenced in Statement: 70.25.117.4.1
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Defined in Statement: 70.25.117.4.2
[+][-] ASM000051 OFFSET [Code] 00001 00001 00000 000000 00000244
Defined in Statement: 70.25.132.1
Referenced in Statement: 70.25.129.1.1
[+][-] ASM000052 OFFSET [Code] 00001 00001 00000 000000 00000244
Defined in Statement: 70.25.132.2
[+][-] ASM000053 OFFSET [Code] 00001 00001 00000 000000 00000230
Defined in Statement: 70.25.129.1.2
[+][-] ASM000054 OFFSET [Code] 00001 00001 00000 000000 00000260
Defined in Statement: 70.25.139.1
Referenced in Statement: 70.25.136.1.1
[+][-] ASM000055 OFFSET [Code] 00001 00001 00000 000000 00000260
Defined in Statement: 70.25.139.2
[+][-] ASM000056 OFFSET [Code] 00001 00001 00000 000000 00000250
Defined in Statement: 70.25.136.1.2
[+][-] ASM000057 OFFSET [Code] 00001 00001 00000 000000 00000298
Defined in Statement: 70.25.159.1
Referenced in Statement: 70.25.155.1.1
[+][-] ASM000058 OFFSET [Code] 00001 00001 00000 000000 00000298
Defined in Statement: 70.25.159.2
[+][-] ASM000059 OFFSET [Code] 00001 00001 00000 000000 0000028C
Defined in Statement: 70.25.155.1.2
[+][-] ASM000060 OFFSET [Code] 00001 00001 00000 000000 000002AC
Defined in Statement: 70.25.165.1.2
[+][-] ASM000061 OFFSET [Code] 00001 00001 00000 000000 000002C8
Defined in Statement: 70.25.177.1
Referenced in Statement: 70.25.172.1.1
[+][-] ASM000062 OFFSET [Code] 00001 00001 00000 000000 000002C8
Defined in Statement: 70.25.177.2
[+][-] ASM000063 OFFSET [Code] 00001 00001 00000 000000 000002B8
Defined in Statement: 70.25.172.1.2
[+][-] ASM000064 OFFSET [Code] 00001 00001 00000 000000 000002DC
Defined in Statement: 70.25.183.3
Referenced in Statement: 70.25.181.1.1.1
[+][-] ASM000065 OFFSET [Code] 00001 00001 00000 000000 000002E0
Defined in Statement: 70.25.185.1
Referenced in Statement: 70.25.183.2
[+][-] ASM000066 OFFSET [Code] 00001 00001 00000 000000 000002D4
Defined in Statement: 70.25.181.1.2
[+][-] ASM000067 OFFSET [Code] 00002 00004 00001 000004 00000504
Defined in Statement: 81.175.4.1
Referenced in Statement: 81.115.1.1
Referenced in Statement: 81.118.1
Referenced in Statement: 81.122.1.1
Referenced in Statement: 81.124.1
Referenced in Statement: 81.162.1.1
Referenced in Statement: 81.165.1
Referenced in Statement: 81.169.1.1
Referenced in Statement: 81.20.1
Referenced in Statement: 81.24.1
Referenced in Statement: 81.43.1
Referenced in Statement: 81.48.1
Referenced in Statement: 81.67.1
Referenced in Statement: 81.72.1
[+][-] ASM000068 OFFSET [Code] 00001 00001 00000 000000 000002F0
Defined in Statement: 81.1.1
[+][-] ASM000069 OFFSET [Code] 00001 00001 00000 000000 000007B0
Defined in Statement: 81.176.1
Referenced in Statement: 81.15.1
Referenced in Statement: 81.37.1
Referenced in Statement: 81.61.1
[+][-] ASM000070 OFFSET [Code] 00001 00001 00000 000000 0000032C
Defined in Statement: 81.25.1
Referenced in Statement: 81.11.1.1
Referenced in Statement: 81.11.1.2
[+][-] ASM000071 OFFSET [Code] 00001 00001 00000 000000 0000032C
Defined in Statement: 81.25.2
[+][-] ASM000072 OFFSET [Code] 00001 00001 00000 000000 0000030C
Defined in Statement: 81.11.1.3
[+][-] ASM000073 OFFSET [Code] 00001 00001 00000 000000 00000318
Defined in Statement: 81.16.1
Referenced in Statement: 81.13.1.1
[+][-] ASM000074 OFFSET [Code] 00001 00001 00000 000000 00000318
Defined in Statement: 81.16.2
[+][-] ASM000075 OFFSET [Code] 00001 00001 00000 000000 00000310
Defined in Statement: 81.13.1.2
[+][-] ASM000076 OFFSET [Code] 00001 00001 00000 000000 00000324
Defined in Statement: 81.21.1
Referenced in Statement: 81.18.1.1
[+][-] ASM000077 OFFSET [Code] 00001 00001 00000 000000 00000324
Defined in Statement: 81.21.2
[+][-] ASM000078 OFFSET [Code] 00001 00001 00000 000000 0000031C
Defined in Statement: 81.18.1.2
[+][-] ASM000079 OFFSET [Code] 00001 00001 00000 000000 00000378
Defined in Statement: 81.49.1
Referenced in Statement: 81.30.1.1
[+][-] ASM000080 OFFSET [Code] 00001 00001 00000 000000 00000378
Defined in Statement: 81.49.2
[+][-] ASM000081 OFFSET [Code] 00001 00001 00000 000000 00000330
Defined in Statement: 81.30.1.2
[+][-] ASM000082 OFFSET [Code] 00001 00001 00000 000000 00000348
Defined in Statement: 81.38.1
Referenced in Statement: 81.33.1.1
[+][-] ASM000083 OFFSET [Code] 00001 00001 00000 000000 00000348
Defined in Statement: 81.38.2
[+][-] ASM000084 OFFSET [Code] 00001 00001 00000 000000 00000338
Defined in Statement: 81.33.1.2
[+][-] ASM000085 OFFSET [Code] 00001 00001 00000 000000 00000360
Defined in Statement: 81.44.1
Referenced in Statement: 81.40.1.1
[+][-] ASM000086 OFFSET [Code] 00001 00001 00000 000000 00000360
Defined in Statement: 81.44.2
[+][-] ASM000087 OFFSET [Code] 00001 00001 00000 000000 0000034C
Defined in Statement: 81.40.1.2
[+][-] ASM000088 OFFSET [Code] 00001 00001 00000 000000 000003C4
Defined in Statement: 81.73.1
Referenced in Statement: 81.54.1.1
[+][-] ASM000089 OFFSET [Code] 00001 00001 00000 000000 000003C4
Defined in Statement: 81.73.2
[+][-] ASM000090 OFFSET [Code] 00001 00001 00000 000000 0000037C
Defined in Statement: 81.54.1.2
[+][-] ASM000091 OFFSET [Code] 00001 00001 00000 000000 00000394
Defined in Statement: 81.62.1
Referenced in Statement: 81.57.1.1
[+][-] ASM000092 OFFSET [Code] 00001 00001 00000 000000 00000394
Defined in Statement: 81.62.2
[+][-] ASM000093 OFFSET [Code] 00001 00001 00000 000000 00000384
Defined in Statement: 81.57.1.2
[+][-] ASM000094 OFFSET [Code] 00001 00001 00000 000000 000003B0
Defined in Statement: 81.68.1
Referenced in Statement: 81.64.1.1
[+][-] ASM000095 OFFSET [Code] 00001 00001 00000 000000 000003B0
Defined in Statement: 81.68.2
[+][-] ASM000096 OFFSET [Code] 00001 00001 00000 000000 00000398
Defined in Statement: 81.64.1.2
[+][-] ASM000097 OFFSET [Code] 00001 00001 00000 000000 00000468
Defined in Statement: 81.125.1
Referenced in Statement: 81.83.1.1
[+][-] ASM000098 OFFSET [Code] 00001 00001 00000 000000 00000468
Defined in Statement: 81.125.2
[+][-] ASM000099 OFFSET [Code] 00001 00001 00000 000000 000003CC
Defined in Statement: 81.83.1.2
[+][-] ASM000100 OFFSET [Code] 00001 00001 00000 000000 000003D0
Defined in Statement: 81.85.1
[+][-] ASM000101 OFFSET [Code] 00001 00001 00000 000000 000003D0
Defined in Statement: 81.85.2
Referenced in Statement: 81.89.1
[+][-] ASM000102 OFFSET [Code] 00001 00001 00000 000000 000003E0
Defined in Statement: 81.89.2
Referenced in Statement: 81.87.1.1
[+][-] ASM000103 OFFSET [Code] 00001 00001 00000 000000 000003D8
Defined in Statement: 81.87.1.2
[+][-] ASM000104 OFFSET [Code] 00001 00001 00000 000000 000003EC
Defined in Statement: 81.93.3
Referenced in Statement: 81.91.1.1
[+][-] ASM000105 OFFSET [Code] 00001 00001 00000 000000 000003FC
Defined in Statement: 81.99.1
Referenced in Statement: 81.93.2
[+][-] ASM000106 OFFSET [Code] 00001 00001 00000 000000 000003E4
Defined in Statement: 81.91.1.2
[+][-] ASM000107 OFFSET [Code] 00001 00001 00000 000000 000003F8
Defined in Statement: 81.96.3
Referenced in Statement: 81.94.1.1
[+][-] ASM000108 OFFSET [Code] 00001 00001 00000 000000 000003FC
Defined in Statement: 81.98.1
Referenced in Statement: 81.96.2
[+][-] ASM000109 OFFSET [Code] 00001 00001 00000 000000 000003F0
Defined in Statement: 81.94.1.2
[+][-] ASM000110 OFFSET [Code] 00001 00001 00000 000000 00000458
Defined in Statement: 81.119.1
Referenced in Statement: 81.108.1.1
[+][-] ASM000111 OFFSET [Code] 00001 00001 00000 000000 00000458
Defined in Statement: 81.119.2
[+][-] ASM000112 OFFSET [Code] 00001 00001 00000 000000 00000420
Defined in Statement: 81.108.1.2
[+][-] ASM000113 OFFSET [Code] 00001 00001 00000 000000 00000444
Defined in Statement: 81.115.1.2
[+][-] ASM000114 OFFSET [Code] 00001 00001 00000 000000 00000460
Defined in Statement: 81.122.1.2
[+][-] ASM000115 OFFSET [Code] 00001 00001 00000 000000 0000046C
Defined in Statement: 81.131.1
[+][-] ASM000116 OFFSET [Code] 00001 00001 00000 000000 0000046C
Defined in Statement: 81.131.2
Referenced in Statement: 81.135.1
[+][-] ASM000117 OFFSET [Code] 00001 00001 00000 000000 0000047C
Defined in Statement: 81.135.2
Referenced in Statement: 81.133.1.1
[+][-] ASM000118 OFFSET [Code] 00001 00001 00000 000000 00000474
Defined in Statement: 81.133.1.2
[+][-] ASM000119 OFFSET [Code] 00001 00001 00000 000000 00000488
Defined in Statement: 81.139.3
Referenced in Statement: 81.137.1.1
[+][-] ASM000120 OFFSET [Code] 00001 00001 00000 000000 00000498
Defined in Statement: 81.145.1
Referenced in Statement: 81.139.2
[+][-] ASM000121 OFFSET [Code] 00001 00001 00000 000000 00000480
Defined in Statement: 81.137.1.2
[+][-] ASM000122 OFFSET [Code] 00001 00001 00000 000000 00000494
Defined in Statement: 81.142.3
Referenced in Statement: 81.140.1.1
[+][-] ASM000123 OFFSET [Code] 00001 00001 00000 000000 00000498
Defined in Statement: 81.144.1
Referenced in Statement: 81.142.2
[+][-] ASM000124 OFFSET [Code] 00001 00001 00000 000000 0000048C
Defined in Statement: 81.140.1.2
[+][-] ASM000125 OFFSET [Code] 00001 00001 00000 000000 000004F8
Defined in Statement: 81.166.1
Referenced in Statement: 81.154.1.1
[+][-] ASM000126 OFFSET [Code] 00001 00001 00000 000000 000004F8
Defined in Statement: 81.166.2
[+][-] ASM000127 OFFSET [Code] 00001 00001 00000 000000 000004BC
Defined in Statement: 81.154.1.2
[+][-] ASM000128 OFFSET [Code] 00001 00001 00000 000000 000004E0
Defined in Statement: 81.162.1.2
[+][-] ASM000129 OFFSET [Code] 00001 00001 00000 000000 00000500
Defined in Statement: 81.169.1.2
[+][-] ASM000130 OFFSET [Code] 00002 00004 00001 000004 00000770
Defined in Statement: 81.175.182.1
Referenced in Statement: 81.175.115.1
Referenced in Statement: 81.175.155.1
Referenced in Statement: 81.175.42.1
Referenced in Statement: 81.175.84.1
[+][-] ASM000131 OFFSET [Code] 00001 00001 00000 000000 00000508
Defined in Statement: 81.175.6.1
Referenced in Statement: 81.175.177.1
Referenced in Statement: 81.175.199.1.2
[+][-] ASM000132 OFFSET [Code] 00001 00001 00000 000000 000007B0
Defined in Statement: 81.175.200.1
Referenced in Statement: 81.175.168.1
Referenced in Statement: 81.175.176.1.1
Referenced in Statement: 81.175.187.1
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Defined in Statement: 81.175.89.3
Referenced in Statement: 81.175.18.1.1.1
[+][-] ASM000134 OFFSET [Code] 00001 00001 00000 000000 00000738
Defined in Statement: 81.175.156.2
Referenced in Statement: 81.175.89.2
[+][-] ASM000135 OFFSET [Code] 00001 00001 00000 000000 0000052C
Defined in Statement: 81.175.18.1.2
[+][-] ASM000136 OFFSET [Code] 00001 00001 00000 000000 00000598
Defined in Statement: 81.175.43.1
Referenced in Statement: 81.175.27.1.1
[+][-] ASM000137 OFFSET [Code] 00001 00001 00000 000000 00000598
Defined in Statement: 81.175.43.2
[+][-] ASM000138 OFFSET [Code] 00001 00001 00000 000000 00000544
Defined in Statement: 81.175.27.1.2
[+][-] ASM000139 OFFSET [Code] 00001 00001 00000 000000 00000560
Defined in Statement: 81.175.32.1
Referenced in Statement: 81.175.29.1.1
[+][-] ASM000140 OFFSET [Code] 00001 00001 00000 000000 00000560
Defined in Statement: 81.175.32.2
[+][-] ASM000141 OFFSET [Code] 00001 00001 00000 000000 0000054C
Defined in Statement: 81.175.29.1.2
[+][-] ASM000142 OFFSET [Code] 00001 00001 00000 000000 0000057C
Defined in Statement: 81.175.36.3
Referenced in Statement: 81.175.33.1.1
[+][-] ASM000143 OFFSET [Code] 00001 00001 00000 000000 0000058C
Defined in Statement: 81.175.39.1
Referenced in Statement: 81.175.36.2
[+][-] ASM000144 OFFSET [Code] 00001 00001 00000 000000 00000564
Defined in Statement: 81.175.33.1.2
[+][-] ASM000145 OFFSET [Code] 00001 00001 00000 000000 000005B4
Defined in Statement: 81.175.55.3
Referenced in Statement: 81.175.52.1.1
[+][-] ASM000146 OFFSET [Code] 00001 00001 00000 000000 000005CC
Defined in Statement: 81.175.61.1
Referenced in Statement: 81.175.55.2
Referenced in Statement: 81.175.58.2
[+][-] ASM000147 OFFSET [Code] 00001 00001 00000 000000 000005A8
Defined in Statement: 81.175.52.1.2
[+][-] ASM000148 OFFSET [Code] 00001 00001 00000 000000 000005C4
Defined in Statement: 81.175.58.3
Referenced in Statement: 81.175.55.4.1.1
[+][-] ASM000149 OFFSET [Code] 00001 00001 00000 000000 000005B8
Defined in Statement: 81.175.55.4.2
[+][-] ASM000150 OFFSET [Code] 00001 00001 00000 000000 000005F0
Defined in Statement: 81.175.71.1
Referenced in Statement: 81.175.68.1.1
[+][-] ASM000151 OFFSET [Code] 00001 00001 00000 000000 000005F0
Defined in Statement: 81.175.71.2
[+][-] ASM000152 OFFSET [Code] 00001 00001 00000 000000 000005E0
Defined in Statement: 81.175.68.1.2
[+][-] ASM000153 OFFSET [Code] 00001 00001 00000 000000 00000610
Defined in Statement: 81.175.78.1
Referenced in Statement: 81.175.75.1.1
[+][-] ASM000154 OFFSET [Code] 00001 00001 00000 000000 00000610
Defined in Statement: 81.175.78.2
[+][-] ASM000155 OFFSET [Code] 00001 00001 00000 000000 000005FC
Defined in Statement: 81.175.75.1.2
[+][-] ASM000156 OFFSET [Code] 00001 00001 00000 000000 00000738
Defined in Statement: 81.175.156.1
Referenced in Statement: 81.175.89.5.1
[+][-] ASM000157 OFFSET [Code] 00001 00001 00000 000000 00000638
Defined in Statement: 81.175.89.5.2
[+][-] ASM000158 OFFSET [Code] 00001 00001 00000 000000 000006A4
Defined in Statement: 81.175.116.1
Referenced in Statement: 81.175.99.1.1.1
[+][-] ASM000159 OFFSET [Code] 00001 00001 00000 000000 000006A4
Defined in Statement: 81.175.116.2
[+][-] ASM000160 OFFSET [Code] 00001 00001 00000 000000 00000650
Defined in Statement: 81.175.99.1.2
[+][-] ASM000161 OFFSET [Code] 00001 00001 00000 000000 00000668
Defined in Statement: 81.175.104.1
Referenced in Statement: 81.175.101.1.1
[+][-] ASM000162 OFFSET [Code] 00001 00001 00000 000000 00000668
Defined in Statement: 81.175.104.2
[+][-] ASM000163 OFFSET [Code] 00001 00001 00000 000000 00000658
Defined in Statement: 81.175.101.1.2
[+][-] ASM000164 OFFSET [Code] 00001 00001 00000 000000 00000684
Defined in Statement: 81.175.108.3
Referenced in Statement: 81.175.105.1.1
[+][-] ASM000165 OFFSET [Code] 00001 00001 00000 000000 00000698
Defined in Statement: 81.175.111.1
Referenced in Statement: 81.175.108.2
[+][-] ASM000166 OFFSET [Code] 00001 00001 00000 000000 0000066C
Defined in Statement: 81.175.105.1.2
[+][-] ASM000167 OFFSET [Code] 00001 00001 00000 000000 000006C0
Defined in Statement: 81.175.127.3
Referenced in Statement: 81.175.124.1.1
[+][-] ASM000168 OFFSET [Code] 00001 00001 00000 000000 000006D8
Defined in Statement: 81.175.133.1
Referenced in Statement: 81.175.127.2
Referenced in Statement: 81.175.130.2
[+][-] ASM000169 OFFSET [Code] 00001 00001 00000 000000 000006B4
Defined in Statement: 81.175.124.1.2
[+][-] ASM000170 OFFSET [Code] 00001 00001 00000 000000 000006D0
Defined in Statement: 81.175.130.3
Referenced in Statement: 81.175.127.4.1
[+][-] ASM000171 OFFSET [Code] 00001 00001 00000 000000 000006C4
Defined in Statement: 81.175.127.4.2
[+][-] ASM000172 OFFSET [Code] 00001 00001 00000 000000 00000700
Defined in Statement: 81.175.142.1
Referenced in Statement: 81.175.139.1.1
[+][-] ASM000173 OFFSET [Code] 00001 00001 00000 000000 00000700
Defined in Statement: 81.175.142.2
[+][-] ASM000174 OFFSET [Code] 00001 00001 00000 000000 000006EC
Defined in Statement: 81.175.139.1.2
[+][-] ASM000175 OFFSET [Code] 00001 00001 00000 000000 0000071C
Defined in Statement: 81.175.149.1
Referenced in Statement: 81.175.146.1.1
[+][-] ASM000176 OFFSET [Code] 00001 00001 00000 000000 0000071C
Defined in Statement: 81.175.149.2
[+][-] ASM000177 OFFSET [Code] 00001 00001 00000 000000 0000070C
Defined in Statement: 81.175.146.1.2
[+][-] ASM000178 OFFSET [Code] 00001 00001 00000 000000 00000754
Defined in Statement: 81.175.169.1
Referenced in Statement: 81.175.165.1.1
[+][-] ASM000179 OFFSET [Code] 00001 00001 00000 000000 00000754
Defined in Statement: 81.175.169.2
[+][-] ASM000180 OFFSET [Code] 00001 00001 00000 000000 00000748
Defined in Statement: 81.175.165.1.2
[+][-] ASM000181 OFFSET [Code] 00001 00001 00000 000000 0000076C
Defined in Statement: 81.175.176.1.2
[+][-] ASM000182 OFFSET [Code] 00001 00001 00000 000000 00000788
Defined in Statement: 81.175.188.1
Referenced in Statement: 81.175.183.1.1
[+][-] ASM000183 OFFSET [Code] 00001 00001 00000 000000 00000788
Defined in Statement: 81.175.188.2
[+][-] ASM000184 OFFSET [Code] 00001 00001 00000 000000 00000778
Defined in Statement: 81.175.183.1.2
[+][-] ASM000185 OFFSET [Code] 00001 00001 00000 000000 0000079C
Defined in Statement: 81.175.194.3
Referenced in Statement: 81.175.192.1.1.1
[+][-] ASM000186 OFFSET [Code] 00001 00001 00000 000000 000007A0
Defined in Statement: 81.175.196.1
Referenced in Statement: 81.175.194.2
[+][-] ASM000187 OFFSET [Code] 00001 00001 00000 000000 00000794
Defined in Statement: 81.175.192.1.2
[+][-] ASM000188 OFFSET [Code] 00001 00001 00000 000000 000007B0
Defined in Statement: 81.175.199.1.3
Referenced in Statement: 81.175.199.1.1
[+][-] CODE OFFSET [Code] 00001 00000 00001 000000 00000000
Defined in Statement: 63.1
[+][-] CYCLE ABSOLUTE 00001 00000 00001 000000 00000C00
Defined in Statement: 61.191
[+][-] CYCLEH ABSOLUTE 00001 00000 00001 000000 00000C80
Defined in Statement: 61.194
[+][-] DUPLKEY OFFSET [Code] 00002 00004 00001 000004 000002E4
Defined in Statement: 74
Referenced in Statement: 70.10.8.1.1
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Defined in Statement: 67.2
Referenced in Statement: 67.1
[+][-] DVASMAVLREMOVE dvasmavlremove OBJECT GLOBAL OFFSET [Code] 00008 00008 00000 000000 000002F0
Defined in Statement: 78.2
Referenced in Statement: 78.1
[+][-] ELF_SHF_ALLOC ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 61.1.13
Referenced in Statement: 63.1
[+][-] ELF_SHF_EXECINSTR ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 61.1.14
Referenced in Statement: 63.1
[+][-] ELF_SHF_WRITE ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 61.1.12
[+][-] ELF_SHT_NOBITS ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 61.1.10
[+][-] ELF_SHT_NOTE ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 61.1.9
[+][-] ELF_SHT_PROGBITS ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 61.1.8
Referenced in Statement: 63.1
[+][-] ELF_STB_GLOBAL ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 61.1.17
[+][-] ELF_STB_LOCAL ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 61.1.16
[+][-] ELF_STB_WEAK ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 61.1.18
[+][-] ELF_STT_FILE ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 61.1.24
[+][-] ELF_STT_FUNC ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 61.1.22
[+][-] ELF_STT_NOTYPE ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 61.1.20
[+][-] ELF_STT_OBJECT ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 61.1.21
[+][-] ELF_STT_SECTION ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 61.1.23
[+][-] F0 ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 61.109
[+][-] F1 ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 61.110
[+][-] F10 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 61.119
[+][-] F11 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 61.120
[+][-] F12 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 61.121
[+][-] F13 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 61.122
[+][-] F14 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 61.123
[+][-] F15 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 61.124
[+][-] F16 ABSOLUTE 00001 00000 00001 000000 00000010
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[+][-] F17 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 61.126
[+][-] F18 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 61.127
[+][-] F19 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 61.128
[+][-] F2 ABSOLUTE 00001 00000 00001 000000 00000002
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[+][-] F20 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 61.129
[+][-] F21 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 61.130
[+][-] F22 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 61.131
[+][-] F23 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 61.132
[+][-] F24 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 61.133
[+][-] F25 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 61.134
[+][-] F26 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 61.135
[+][-] F27 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 61.136
[+][-] F28 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 61.137
[+][-] F29 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 61.138
[+][-] F3 ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 61.112
[+][-] F30 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 61.139
[+][-] F31 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 61.140
[+][-] F4 ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 61.113
[+][-] F5 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 61.114
[+][-] F6 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 61.115
[+][-] F7 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 61.116
[+][-] F8 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 61.117
[+][-] F9 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 61.118
[+][-] FA0 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 61.154
[+][-] FA1 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 61.155
[+][-] FA2 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 61.156
[+][-] FA3 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 61.157
[+][-] FA4 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 61.158
[+][-] FA5 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 61.159
[+][-] FA6 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 61.160
[+][-] FA7 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 61.161
[+][-] FALSE ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 61.1.2
[+][-] FCSR ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 61.190
[+][-] FFLAGS ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 61.188
[+][-] FRM ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 61.189
[+][-] FS0 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 61.152
[+][-] FS1 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 61.153
[+][-] FS10 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 61.170
[+][-] FS11 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 61.171
[+][-] FS2 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 61.162
[+][-] FS3 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 61.163
[+][-] FS4 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 61.164
[+][-] FS5 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 61.165
[+][-] FS6 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 61.166
[+][-] FS7 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 61.167
[+][-] FS8 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 61.168
[+][-] FS9 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 61.169
[+][-] FT0 ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 61.144
[+][-] FT1 ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 61.145
[+][-] FT10 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 61.174
[+][-] FT11 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 61.175
[+][-] FT2 ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 61.146
[+][-] FT3 ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 61.147
[+][-] FT4 ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 61.148
[+][-] FT5 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 61.149
[+][-] FT6 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 61.150
[+][-] FT7 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 61.151
[+][-] FT8 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 61.172
[+][-] FT9 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 61.173
[+][-] GP ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 61.77
[+][-] INSTRET ABSOLUTE 00001 00000 00001 000000 00000C02
Defined in Statement: 61.193
[+][-] INSTRETH ABSOLUTE 00001 00000 00001 000000 00000C82
Defined in Statement: 61.196
[+][-] NAPIER FLOAT 00001 00000 00001 000000 2.71828182845904523536028747132.71828182845904523536028747135266249775725
Defined in Statement: 61.1.6
[+][-] NO ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 61.1.4
[+][-] PI FLOAT 00001 00000 00001 000000 3.14159265358979323846264338323.14159265358979323846264338327950288419717
Defined in Statement: 61.1.5
[+][-] R0 ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 61.5
[+][-] R1 ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 61.6
[+][-] R10 ABSOLUTE 00001 00000 00001 000000 0000000A
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[+][-] R11 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 61.16
[+][-] R12 ABSOLUTE 00001 00000 00001 000000 0000000C
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[+][-] R13 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 61.18
[+][-] R14 ABSOLUTE 00001 00000 00001 000000 0000000E
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[+][-] R15 ABSOLUTE 00001 00000 00001 000000 0000000F
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[+][-] R16 ABSOLUTE 00001 00000 00001 000000 00000010
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[+][-] R17 ABSOLUTE 00001 00000 00001 000000 00000011
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[+][-] R18 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 61.23
[+][-] R19 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 61.24
[+][-] R2 ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 61.7
[+][-] R20 ABSOLUTE 00001 00000 00001 000000 00000014
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[+][-] R21 ABSOLUTE 00001 00000 00001 000000 00000015
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[+][-] R22 ABSOLUTE 00001 00000 00001 000000 00000016
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[+][-] R23 ABSOLUTE 00001 00000 00001 000000 00000017
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[+][-] R24 ABSOLUTE 00001 00000 00001 000000 00000018
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[+][-] R25 ABSOLUTE 00001 00000 00001 000000 00000019
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[+][-] R26 ABSOLUTE 00001 00000 00001 000000 0000001A
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[+][-] R27 ABSOLUTE 00001 00000 00001 000000 0000001B
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[+][-] R28 ABSOLUTE 00001 00000 00001 000000 0000001C
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[+][-] R29 ABSOLUTE 00001 00000 00001 000000 0000001D
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[+][-] R3 ABSOLUTE 00001 00000 00001 000000 00000003
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[+][-] R30 ABSOLUTE 00001 00000 00001 000000 0000001E
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[+][-] R31 ABSOLUTE 00001 00000 00001 000000 0000001F
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[+][-] R4 ABSOLUTE 00001 00000 00001 000000 00000004
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[+][-] R5 ABSOLUTE 00001 00000 00001 000000 00000005
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[+][-] R6 ABSOLUTE 00001 00000 00001 000000 00000006
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[+][-] R7 ABSOLUTE 00001 00000 00001 000000 00000007
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[+][-] R8 ABSOLUTE 00001 00000 00001 000000 00000008
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[+][-] R9 ABSOLUTE 00001 00000 00001 000000 00000009
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[+][-] RA ABSOLUTE 00001 00000 00001 000000 00000001
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Referenced in Statement: 72.1
Referenced in Statement: 75.1
Referenced in Statement: 82.1
[+][-] RM_DYN ABSOLUTE 00001 00000 00001 000000 00000007
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[+][-] RM_RDN ABSOLUTE 00001 00000 00001 000000 00000002
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[+][-] RM_RMM ABSOLUTE 00001 00000 00001 000000 00000004
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[+][-] RM_RNE ABSOLUTE 00001 00000 00001 000000 00000000
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[+][-] RM_RTZ ABSOLUTE 00001 00000 00001 000000 00000001
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[+][-] RM_RUP ABSOLUTE 00001 00000 00001 000000 00000003
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[+][-] S0 ABSOLUTE 00001 00000 00001 000000 00000008
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[+][-] S1 ABSOLUTE 00001 00000 00001 000000 00000009
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[+][-] S10 ABSOLUTE 00001 00000 00001 000000 0000001A
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[+][-] S11 ABSOLUTE 00001 00000 00001 000000 0000001B
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[+][-] S2 ABSOLUTE 00001 00000 00001 000000 00000012
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[+][-] S3 ABSOLUTE 00001 00000 00001 000000 00000013
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[+][-] S4 ABSOLUTE 00001 00000 00001 000000 00000014
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[+][-] S5 ABSOLUTE 00001 00000 00001 000000 00000015
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[+][-] S6 ABSOLUTE 00001 00000 00001 000000 00000016
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[+][-] S7 ABSOLUTE 00001 00000 00001 000000 00000017
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[+][-] S9 ABSOLUTE 00001 00000 00001 000000 00000019
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[+][-] SP ABSOLUTE 00001 00000 00001 000000 00000002
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[+][-] T0 ABSOLUTE 00001 00000 00001 000000 00000005
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Referenced in Statement: 70.1
Referenced in Statement: 70.11
Referenced in Statement: 70.12.1.1
Referenced in Statement: 70.14.1
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Referenced in Statement: 70.17.1.1
Referenced in Statement: 70.19.1
Referenced in Statement: 70.2.1.1
Referenced in Statement: 70.23
Referenced in Statement: 70.25.10
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Referenced in Statement: 70.25.101.2
Referenced in Statement: 70.25.101.3
Referenced in Statement: 70.25.11.1
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Referenced in Statement: 70.25.143.3
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Referenced in Statement: 70.25.34.3
Referenced in Statement: 70.25.4.1
Referenced in Statement: 70.25.7.1
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Referenced in Statement: 70.25.77.3
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Referenced in Statement: 70.4.2
Referenced in Statement: 70.9.1
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Referenced in Statement: 81.175.125.1
Referenced in Statement: 81.175.128.1
Referenced in Statement: 81.175.131.1.1
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Referenced in Statement: 81.175.148.3
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Referenced in Statement: 81.175.53.1
Referenced in Statement: 81.175.56.1
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Referenced in Statement: 81.175.70.2
Referenced in Statement: 81.175.70.3
Referenced in Statement: 81.175.76
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Referenced in Statement: 81.175.77.3
Referenced in Statement: 81.175.77.4
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----- End of DVASM listing -----
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