//MACRO     Avl.node       
//--------------------------------------------------------------------------------------------------
//
//  @ CopyRight Roberti & Parau Enterprises, Inc.  2021-2023
//
//  This work is licensed under the Creative Commons Attribution-NoDerivatives 4.0 International License.
//  To view a copy of this license, visit http://creativecommons.org/licenses/by-nd/4.0/
//   or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.
//
//--------------------------------------------------------------------------------------------------
//    
    //
    //  Get word type
    //
    eval(DVASM.getEnv()[4]);
    var wrd= abiWID + "WRD";
    
    //
    //  Generate anchor mapping when no label
    //
	if {Lable === null) {
\				#wrd	0[3]								// Space for AVL tree node
		return;
	}

    //
    //  Generate anchor mapping with label
    //
\#Label     	#wrd    0[0]                                // Start of node pointer fields
\															// Always DWRD aligned
\#Label..left   #wrd    0                                   // Node pointer to left child
\#Label..parent #wrd    0                                   // Node pointer to parent
\//
\//  Low 3 bits of parent link are used as link and balance flags as follows:
\//    Bit 1-0 -> 0bx00 (0) on when node right subtree is one deeper than left subtree
\//    Bit 1-0 -> 0bx01 (1) on when node right subtree and left subtree have equal depth
\//    Bit 1-0 -> 0bx10 (2) on when node left subtree is one deeper than right subtree
\//    Bit 1-0 -> 0bx11 INVALID - this is a state error
\//    Bit 2   -> 0b0xx when parent link belongs to parent right child
\//    Bit 2   -> 0b1xx when parent link belongs to parent left child
\//
\//    !!! Node address MUST BE 8 BYTE ALIGNED in order to use parent link 3 low bits !!!
\#Label..right #wrd    0                                    // Node pointer to right child