//MACRO Hash.init Anchor, Vector, VectSizeExp, CellSizeExp, WReg[2] //-------------------------------------------------------------------------------------------------- // // @ CopyRight Roberti & Parau Enterprises, Inc. 2021-2023 // // This work is licensed under the Creative Commons Attribution-NoDerivatives 4.0 International License. // To view a copy of this license, visit http://creativecommons.org/licenses/by-nd/4.0/ // or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. // //-------------------------------------------------------------------------------------------------- // // // Get load/store MIs and word length // eval(DVASM.getEnv()[4]); var ld= "L" + abiWID; var st= "S" + abiWID; var wl= abiWLen; var WReg0= WReg[0]; var WReg1= WReg[1]; var primeLabel= DVASM.getNewLabel(); // // Set literal vector of primes expressed as add on to 2**31-1 (XLEN == 32) or 2**62 (XLEN == 64) // if (abiWID == "D") { \#primeLabel ADDLITERAL WRD_8, /> \ !"0x9E3779B97F4A7C15,0x00B800A200600040,0x0196017E01620108,0x01F201BA01A8019E," /> \ !"0x02A00240022801F6,0x031802E802BE02A6,0x043603900388031E,0x04FE04800462043C," /> \ !"0x063A05F805760540,0x0694067806520648,0x075C06D006C006B2,0x07DE07AA0790077E," /> \ !"0x0828081A07F607F0,0x08B2089E086A0858,0x0A0609E408D008C2,0x0ABA0AAE0A920A38," /> \ !"0x0B460B1C0B0A0AC6,0x0B920B7A0B700B58,0x0CC40C540C060BA0,0x0D720D120CF60CD2," /> \ !"0x0DCE0DC20D9C0D74,0x0E700E400E0E0E02,0x0ED60ED40ECA0EA0,0x0FDE0F9C0F600F58," /> \ !"0x101210060FFC0FE4,0x10C8108C10781044,0x112C1122111010E4,0x11B811B61192118C," /> \ !"0x12301228120A11FE,0x131812DC1296123A,0x13A413A213981396,0x1440143A142013E0," /> \ !"0x15F6154614A4147A" // Add literal vector with deltas from base prime } else { \#primeLabel ADDLITERAL WRD_8, /> \ !"0x000000009E3779B9,0x002C002800220014,0x008C0052003A0034,0x00EE00E600B600A4," /> \ !"0x01520130012A00F2,0x020201D801CC019C,0x0284027A02480212,0x031A02DE02BC02B4," /> \ !"0x038E0368034A0346,0x03C803AC03A6039A,0x03EC03E003D603D4,0x0458044E042803FE," /> \ !"0x049A048A0488047E,0x04DC04B804A6049C,0x05320512050E0508,0x056C055A054E053C," /> \ !"0x05C205B605B40586,0x063A061C05DA05C8,0x06740656064C0640,0x06BC06A4068E0688," /> \ !"0x070006EE06D406CA,0x07480742070C070A,0x07CA07C607960766,0x080C07E207DC07D2," /> \ !"0x086E085408360824,0x08C208C00898088C,0x091A08EA08E608E0,0x0986096409440922," /> \ !"0x09F809B209AA0992,0x0A400A3C0A1C0A16,0x0B120AF40ADE0A58,0x0B540B420B360B18," /> \ !"0x0BC20BC00B980B80" // Add literal vector with deltas from base prime } // // Set Label if specified // if (Label !== "") \#Label BYTE 0[0] // // Store vector addr in anchor // \ #st #Vector, #Anchor // Store vector addr in anchor // // Compute hash shift and store it in anchor // \ LI #WReg1, #wl*8 // Load word width in bits \ SUB #WReg1, #VectSizeExp // Compute hash shift \ SW #WReg1, (2*#wl)+#Anchor // Store it as half word // // Store hash cell size exponent as right shift // \ SW #CellSizeExp, (2*#wl+4)+#Anchor // Store hash cell size exponent as right shift // // Select prime number randomly // \ RDCYCLE #WReg0 // Get number of CPU cycles as a unbiased random number \ ANDI #WReg0, 0b1111111 // Keep only the low 7 bits \ SLLI #WReg0, 1 // Multiply by two - offset into possible prime vectors \ ADDI #WReg1, 8+#primeLabel // Load addr of prime vector \ ADD #WReg1, #WReg0 // Load selected prime add on addr \ LH #WReg1, 0[#WReg1] // Load selected prime delta \ #ld #WReg0, #primeLabel // Load base number \ ADD #WReg0, #WReg1 // Add the prime delta \ #st #WReg0, #wl+#Anchor // Store it in anchor