DVASM Listing for Input File: /TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/examples/riscv-heapsort/dvasmsortstring.asm
DVASM execution completed on: Wed Aug 30 22:44:15 EDT 2023
--- Log Start
Framework JAR file is [file:/TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/code-and-manuals/dvasm.v1-r0.1.jar]
User macro directory[1] is: [/TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/examples/riscv-heapsort]
Architecture JAR file selected is [file:/TAREA/PROJECTS/DVASM-REPO/v1-r0.1/downloads/code-and-manuals/dvasm.v1-r0.1.jar]
No architecture extension used
Parse elapsed time is: 1514 milliseconds
Input parsing completed succesfully
Dependencies preprocessing completed successfully
Dependencies resolution completed successfully
Code generation completed successfully
Dependencies resolution completed successfully
Code generation completed successfully
Code generation elapsed time is: 37 milliseconds
--- Log End
1 | //--------------------------------------------------------------------------------------------------
2 | //
3 | // @ CopyRight Roberti & Parau Enterprises, Inc. 2021-2023
4 | //
5 | // This work is licensed under the Creative Commons Attribution 4.0 International License.
6 | // To view a copy of this license, visit http://creativecommons.org/licenses/by/4.0/
7 | // or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.
8 | //
9 | //--------------------------------------------------------------------------------------------------
10 | //
11 | // This code sort a vector of 64 bits addresses, each pointing to a null terminated string
12 | // The sort is in ascending order, and is done using macro HEAPSORT from the standard
13 | // DaVinci assembler RISC-V module.
14 | // It can be called as a function by C code generated by the GNU compiler
15 | // or any GNU compatible compiler
16 | //
17 | // The code is divided into two sections:
18 | //
19 | // 1. The macro that carries out all string comparisons
20 | //
21 | // 2. The SECTION that use macro HEAPSORT to actually sort the vector
22 | //
23 | //--------------------------------------------------------------------------------------------------
24 | //
25 | // If this is the first time you view a Da Vinci Assembler listing, here are some tips
26 | //
27 | // - As you move the cursor around, if you see the color under the cursor changing, click
28 | // on it and additional data will be shown
29 | //
30 | // - If at the beginning of a line you see [+] click on it and it will expand in multiple
31 | // lines. If you do this on a macro it will expand the macro generated code
32 | // You could get the same result by right clicking on the line.
33 | //
34 | //--------------------------------------------------------------------------------------------------
35 | //
36 | // Define the comparison macro that is used by the HEAPSORT macro
37 | // This is a specialize STRING.COMP to optimize brnaching
38 | //
39 | #MACRO
40 | //MACRO CompStr R1, R2, EqualFlag{boolean}, BranchLabel, WReg[4-32]
41 |
42 | var addr1= WReg[0];
43 | var addr2= WReg[1];
44 | var wreg0= WReg[2];
45 | var wreg1= WReg[3];
46 |
47 | \#Label MV #addr1, #R1 // Copy string 1 address
48 | \ MV #addr2, #R2 // Copy string 2 address
49 | \ WHILE // Start DO block
50 | \ LBU #wreg0, 0[#addr1] // Load first string byte
51 | \ LBU #wreg1, 0[#addr2] // Load second string byte
52 |
53 | \ IF (#wreg0 < #wreg1), GOTO, ID= #BranchLabel // Done less than
54 | \ IF (#wreg0 > #wreg1), BREAK // Done if greater than
55 |
56 | if (EqualFlag)
57 | \ IF ( #wreg1 == 0 ), GOTO, ID= #BranchLabel // Equal condition with equal flag
58 | else
59 | \ IF ( #wreg1 == 0 ), BREAK // Done - equal strings
60 |
61 | \ ADDI #addr1, 1 // Get next char address (string 1)
62 | \ ADDI #addr2, 1 // Get next char address (string 2)
63 | \ ENDWHILE
64 | #END
65 | //
66 | // Actual code starts here
67 | //
68 | SETENV "RISCV", "RV64I:a,c,d,m,n,zicsr,zifencei", "LP64D", "linux"
Architecture is................................. RISCV
Number of registers............................. 32
Register bit length (XLEN)...................... 64
Number of floating registers.................... 32
Floating register bit length (FLEN)............. 64
(A) atomic extension............................ Used
(C) two byte opCode encoding extension.......... Used
(M) integer multiply/divide extension........... Used
(N) user level interrupt extension.............. Used
(ZTSO) total store ordering..................... Not Used
(ZICSR) control/status registers extension...... Used
(ZIFENCEI) instruction fetch fence extension.... Used
ABI............................................. LP64D
Operating System................................ LINUX
69 | // Define the srchitecture
[+][-] 70 | BaseDef // Include standard definitions
Macro [BASEDEF] source location is [JAR: /arch/RISCV/macros/BaseDef.mac]
[+][-] 70.1 |BASEDEF FrameWorkDef // Include DVASM framework base definitions
Macro [FRAMEWORKDEF] source location is [JAR: /framework/macros/FrameWorkDef.mac]
70.1.1 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 TRUE EQU 1
70.1.2 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 FALSE EQU 0
70.1.3 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 YES EQU 1
70.1.4 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 NO EQU 0
70.1.5 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF FLOFLOAT 3.14159265358 3.14159265358979323846264338327950288419717 PI EQU 3.14159265358979323846264338327950288419716939937510582097494459230781640628620899
70.1.6 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF FLOFLOAT 2.71828182845 2.71828182845904523536028747135266249775725 NAPIER EQU 2.71828182845904523536028747135266249775724709369995957496696762772407663035354759
70.1.6 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid section types
70.1.8 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_SHT_PROGBITS EQU 1
70.1.9 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000007 ELF_SHT_NOTE EQU 7
70.1.10 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000008 ELF_SHT_NOBITS EQU 8
70.1.10 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid section attributes
70.1.12 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_SHF_WRITE EQU 1
70.1.13 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000002 ELF_SHF_ALLOC EQU 2
70.1.14 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000004 ELF_SHF_EXECINSTR EQU 4
70.1.14 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid symbol bindings
70.1.16 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 ELF_STB_LOCAL EQU 0
70.1.17 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_STB_GLOBAL EQU 1
70.1.18 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000002 ELF_STB_WEAK EQU 2
70.1.18 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF // Define valid symbol types
70.1.20 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000000 ELF_STT_NOTYPE EQU 0
70.1.21 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000001 ELF_STT_OBJECT EQU 1
70.1.22 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000002 ELF_STT_FUNC EQU 2
70.1.23 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000003 ELF_STT_SECTION EQU 3
70.1.24 DEF:FRAMEWORKDEF|BASEDEF:FRAMEWORKDEF ABSABSOLUTE 00000004 ELF_STT_FILE EQU 4
70.2 |BASEDEF //
70.3 |BASEDEF // Base register definitions "R" prefix
70.4 |BASEDEF //
70.5 |BASEDEF ABSABSOLUTE 00000000 r0 EQU 0
70.6 |BASEDEF ABSABSOLUTE 00000001 r1 EQU 1
70.7 |BASEDEF ABSABSOLUTE 00000002 r2 EQU 2
70.8 |BASEDEF ABSABSOLUTE 00000003 r3 EQU 3
70.9 |BASEDEF ABSABSOLUTE 00000004 r4 EQU 4
70.10 |BASEDEF ABSABSOLUTE 00000005 r5 EQU 5
70.11 |BASEDEF ABSABSOLUTE 00000006 r6 EQU 6
70.12 |BASEDEF ABSABSOLUTE 00000007 r7 EQU 7
70.13 |BASEDEF ABSABSOLUTE 00000008 r8 EQU 8
70.14 |BASEDEF ABSABSOLUTE 00000009 r9 EQU 9
70.15 |BASEDEF ABSABSOLUTE 0000000A r10 EQU 10
70.16 |BASEDEF ABSABSOLUTE 0000000B r11 EQU 11
70.17 |BASEDEF ABSABSOLUTE 0000000C r12 EQU 12
70.18 |BASEDEF ABSABSOLUTE 0000000D r13 EQU 13
70.19 |BASEDEF ABSABSOLUTE 0000000E r14 EQU 14
70.20 |BASEDEF ABSABSOLUTE 0000000F r15 EQU 15
70.21 |BASEDEF ABSABSOLUTE 00000010 r16 EQU 16
70.22 |BASEDEF ABSABSOLUTE 00000011 r17 EQU 17
70.23 |BASEDEF ABSABSOLUTE 00000012 r18 EQU 18
70.24 |BASEDEF ABSABSOLUTE 00000013 r19 EQU 19
70.25 |BASEDEF ABSABSOLUTE 00000014 r20 EQU 20
70.26 |BASEDEF ABSABSOLUTE 00000015 r21 EQU 21
70.27 |BASEDEF ABSABSOLUTE 00000016 r22 EQU 22
70.28 |BASEDEF ABSABSOLUTE 00000017 r23 EQU 23
70.29 |BASEDEF ABSABSOLUTE 00000018 r24 EQU 24
70.30 |BASEDEF ABSABSOLUTE 00000019 r25 EQU 25
70.31 |BASEDEF ABSABSOLUTE 0000001A r26 EQU 26
70.32 |BASEDEF ABSABSOLUTE 0000001B r27 EQU 27
70.33 |BASEDEF ABSABSOLUTE 0000001C r28 EQU 28
70.34 |BASEDEF ABSABSOLUTE 0000001D r29 EQU 29
70.35 |BASEDEF ABSABSOLUTE 0000001E r30 EQU 30
70.36 |BASEDEF ABSABSOLUTE 0000001F r31 EQU 31
70.37 |BASEDEF //
70.38 |BASEDEF // Base register definitions "X" prefix
70.39 |BASEDEF //
70.40 |BASEDEF ABSABSOLUTE 00000000 x0 EQU 0
70.41 |BASEDEF ABSABSOLUTE 00000001 x1 EQU 1
70.42 |BASEDEF ABSABSOLUTE 00000002 x2 EQU 2
70.43 |BASEDEF ABSABSOLUTE 00000003 x3 EQU 3
70.44 |BASEDEF ABSABSOLUTE 00000004 x4 EQU 4
70.45 |BASEDEF ABSABSOLUTE 00000005 x5 EQU 5
70.46 |BASEDEF ABSABSOLUTE 00000006 x6 EQU 6
70.47 |BASEDEF ABSABSOLUTE 00000007 x7 EQU 7
70.48 |BASEDEF ABSABSOLUTE 00000008 x8 EQU 8
70.49 |BASEDEF ABSABSOLUTE 00000009 x9 EQU 9
70.50 |BASEDEF ABSABSOLUTE 0000000A x10 EQU 10
70.51 |BASEDEF ABSABSOLUTE 0000000B x11 EQU 11
70.52 |BASEDEF ABSABSOLUTE 0000000C x12 EQU 12
70.53 |BASEDEF ABSABSOLUTE 0000000D x13 EQU 13
70.54 |BASEDEF ABSABSOLUTE 0000000E x14 EQU 14
70.55 |BASEDEF ABSABSOLUTE 0000000F x15 EQU 15
70.56 |BASEDEF ABSABSOLUTE 00000010 x16 EQU 16
70.57 |BASEDEF ABSABSOLUTE 00000011 x17 EQU 17
70.58 |BASEDEF ABSABSOLUTE 00000012 x18 EQU 18
70.59 |BASEDEF ABSABSOLUTE 00000013 x19 EQU 19
70.60 |BASEDEF ABSABSOLUTE 00000014 x20 EQU 20
70.61 |BASEDEF ABSABSOLUTE 00000015 x21 EQU 21
70.62 |BASEDEF ABSABSOLUTE 00000016 x22 EQU 22
70.63 |BASEDEF ABSABSOLUTE 00000017 x23 EQU 23
70.64 |BASEDEF ABSABSOLUTE 00000018 x24 EQU 24
70.65 |BASEDEF ABSABSOLUTE 00000019 x25 EQU 25
70.66 |BASEDEF ABSABSOLUTE 0000001A x26 EQU 26
70.67 |BASEDEF ABSABSOLUTE 0000001B x27 EQU 27
70.68 |BASEDEF ABSABSOLUTE 0000001C x28 EQU 28
70.69 |BASEDEF ABSABSOLUTE 0000001D x29 EQU 29
70.70 |BASEDEF ABSABSOLUTE 0000001E x30 EQU 30
70.71 |BASEDEF ABSABSOLUTE 0000001F x31 EQU 31
70.72 |BASEDEF //
70.73 |BASEDEF // Alternate ABI register definitions
70.74 |BASEDEF //
70.75 |BASEDEF ABSABSOLUTE 00000001 ra EQU 1
70.76 |BASEDEF ABSABSOLUTE 00000002 sp EQU 2
70.77 |BASEDEF ABSABSOLUTE 00000003 gp EQU 3
70.78 |BASEDEF ABSABSOLUTE 00000004 tp EQU 4
70.79 |BASEDEF ABSABSOLUTE 00000005 t0 EQU 5
70.80 |BASEDEF ABSABSOLUTE 00000006 t1 EQU 6
70.81 |BASEDEF ABSABSOLUTE 00000007 t2 EQU 7
70.82 |BASEDEF ABSABSOLUTE 00000008 s0 EQU 8
70.83 |BASEDEF ABSABSOLUTE 00000009 s1 EQU 9
70.84 |BASEDEF ABSABSOLUTE 0000000A a0 EQU 10
70.85 |BASEDEF ABSABSOLUTE 0000000B a1 EQU 11
70.86 |BASEDEF ABSABSOLUTE 0000000C a2 EQU 12
70.87 |BASEDEF ABSABSOLUTE 0000000D a3 EQU 13
70.88 |BASEDEF ABSABSOLUTE 0000000E a4 EQU 14
70.89 |BASEDEF ABSABSOLUTE 0000000F a5 EQU 15
70.90 |BASEDEF ABSABSOLUTE 00000010 a6 EQU 16
70.91 |BASEDEF ABSABSOLUTE 00000011 a7 EQU 17
70.92 |BASEDEF ABSABSOLUTE 00000012 s2 EQU 18
70.93 |BASEDEF ABSABSOLUTE 00000013 s3 EQU 19
70.94 |BASEDEF ABSABSOLUTE 00000014 s4 EQU 20
70.95 |BASEDEF ABSABSOLUTE 00000015 s5 EQU 21
70.96 |BASEDEF ABSABSOLUTE 00000016 s6 EQU 22
70.97 |BASEDEF ABSABSOLUTE 00000017 s7 EQU 23
70.98 |BASEDEF ABSABSOLUTE 00000018 s8 EQU 24
70.99 |BASEDEF ABSABSOLUTE 00000019 s9 EQU 25
70.100 |BASEDEF ABSABSOLUTE 0000001A s10 EQU 26
70.101 |BASEDEF ABSABSOLUTE 0000001B s11 EQU 27
70.102 |BASEDEF ABSABSOLUTE 0000001C t3 EQU 28
70.103 |BASEDEF ABSABSOLUTE 0000001D t4 EQU 29
70.104 |BASEDEF ABSABSOLUTE 0000001E t5 EQU 30
70.105 |BASEDEF ABSABSOLUTE 0000001F t6 EQU 31
70.106 |BASEDEF //
70.107 |BASEDEF // Floating register definitions
70.108 |BASEDEF //
70.109 |BASEDEF ABSABSOLUTE 00000000 f0 EQU 0
70.110 |BASEDEF ABSABSOLUTE 00000001 f1 EQU 1
70.111 |BASEDEF ABSABSOLUTE 00000002 f2 EQU 2
70.112 |BASEDEF ABSABSOLUTE 00000003 f3 EQU 3
70.113 |BASEDEF ABSABSOLUTE 00000004 f4 EQU 4
70.114 |BASEDEF ABSABSOLUTE 00000005 f5 EQU 5
70.115 |BASEDEF ABSABSOLUTE 00000006 f6 EQU 6
70.116 |BASEDEF ABSABSOLUTE 00000007 f7 EQU 7
70.117 |BASEDEF ABSABSOLUTE 00000008 f8 EQU 8
70.118 |BASEDEF ABSABSOLUTE 00000009 f9 EQU 9
70.119 |BASEDEF ABSABSOLUTE 0000000A f10 EQU 10
70.120 |BASEDEF ABSABSOLUTE 0000000B f11 EQU 11
70.121 |BASEDEF ABSABSOLUTE 0000000C f12 EQU 12
70.122 |BASEDEF ABSABSOLUTE 0000000D f13 EQU 13
70.123 |BASEDEF ABSABSOLUTE 0000000E f14 EQU 14
70.124 |BASEDEF ABSABSOLUTE 0000000F f15 EQU 15
70.125 |BASEDEF ABSABSOLUTE 00000010 f16 EQU 16
70.126 |BASEDEF ABSABSOLUTE 00000011 f17 EQU 17
70.127 |BASEDEF ABSABSOLUTE 00000012 f18 EQU 18
70.128 |BASEDEF ABSABSOLUTE 00000013 f19 EQU 19
70.129 |BASEDEF ABSABSOLUTE 00000014 f20 EQU 20
70.130 |BASEDEF ABSABSOLUTE 00000015 f21 EQU 21
70.131 |BASEDEF ABSABSOLUTE 00000016 f22 EQU 22
70.132 |BASEDEF ABSABSOLUTE 00000017 f23 EQU 23
70.133 |BASEDEF ABSABSOLUTE 00000018 f24 EQU 24
70.134 |BASEDEF ABSABSOLUTE 00000019 f25 EQU 25
70.135 |BASEDEF ABSABSOLUTE 0000001A f26 EQU 26
70.136 |BASEDEF ABSABSOLUTE 0000001B f27 EQU 27
70.137 |BASEDEF ABSABSOLUTE 0000001C f28 EQU 28
70.138 |BASEDEF ABSABSOLUTE 0000001D f29 EQU 29
70.139 |BASEDEF ABSABSOLUTE 0000001E f30 EQU 30
70.140 |BASEDEF ABSABSOLUTE 0000001F f31 EQU 31
70.141 |BASEDEF //
70.142 |BASEDEF // Alternate ABI floating register definitions
70.143 |BASEDEF //
70.144 |BASEDEF ABSABSOLUTE 00000000 ft0 EQU 0
70.145 |BASEDEF ABSABSOLUTE 00000001 ft1 EQU 1
70.146 |BASEDEF ABSABSOLUTE 00000002 ft2 EQU 2
70.147 |BASEDEF ABSABSOLUTE 00000003 ft3 EQU 3
70.148 |BASEDEF ABSABSOLUTE 00000004 ft4 EQU 4
70.149 |BASEDEF ABSABSOLUTE 00000005 ft5 EQU 5
70.150 |BASEDEF ABSABSOLUTE 00000006 ft6 EQU 6
70.151 |BASEDEF ABSABSOLUTE 00000007 ft7 EQU 7
70.152 |BASEDEF ABSABSOLUTE 00000008 fs0 EQU 8
70.153 |BASEDEF ABSABSOLUTE 00000009 fs1 EQU 9
70.154 |BASEDEF ABSABSOLUTE 0000000A fa0 EQU 10
70.155 |BASEDEF ABSABSOLUTE 0000000B fa1 EQU 11
70.156 |BASEDEF ABSABSOLUTE 0000000C fa2 EQU 12
70.157 |BASEDEF ABSABSOLUTE 0000000D fa3 EQU 13
70.158 |BASEDEF ABSABSOLUTE 0000000E fa4 EQU 14
70.159 |BASEDEF ABSABSOLUTE 0000000F fa5 EQU 15
70.160 |BASEDEF ABSABSOLUTE 00000010 fa6 EQU 16
70.161 |BASEDEF ABSABSOLUTE 00000011 fa7 EQU 17
70.162 |BASEDEF ABSABSOLUTE 00000012 fs2 EQU 18
70.163 |BASEDEF ABSABSOLUTE 00000013 fs3 EQU 19
70.164 |BASEDEF ABSABSOLUTE 00000014 fs4 EQU 20
70.165 |BASEDEF ABSABSOLUTE 00000015 fs5 EQU 21
70.166 |BASEDEF ABSABSOLUTE 00000016 fs6 EQU 22
70.167 |BASEDEF ABSABSOLUTE 00000017 fs7 EQU 23
70.168 |BASEDEF ABSABSOLUTE 00000018 fs8 EQU 24
70.169 |BASEDEF ABSABSOLUTE 00000019 fs9 EQU 25
70.170 |BASEDEF ABSABSOLUTE 0000001A fs10 EQU 26
70.171 |BASEDEF ABSABSOLUTE 0000001B fs11 EQU 27
70.172 |BASEDEF ABSABSOLUTE 0000001C ft8 EQU 28
70.173 |BASEDEF ABSABSOLUTE 0000001D ft9 EQU 29
70.174 |BASEDEF ABSABSOLUTE 0000001E ft10 EQU 30
70.175 |BASEDEF ABSABSOLUTE 0000001F ft11 EQU 31
70.176 |BASEDEF //
70.177 |BASEDEF // Define Round Methods for Floating Point Arithmetic
70.178 |BASEDEF //
70.179 |BASEDEF ABSABSOLUTE 00000000 rm_rne EQU 0
70.180 |BASEDEF ABSABSOLUTE 00000001 rm_rtz EQU 1
70.181 |BASEDEF ABSABSOLUTE 00000002 rm_rdn EQU 2
70.182 |BASEDEF ABSABSOLUTE 00000003 rm_rup EQU 3
70.183 |BASEDEF ABSABSOLUTE 00000004 rm_rmm EQU 4
70.184 |BASEDEF ABSABSOLUTE 00000007 rm_dyn EQU 7
70.185 |BASEDEF //
70.186 |BASEDEF // Control registers
70.187 |BASEDEF //
70.188 |BASEDEF ABSABSOLUTE 00000001 fflags EQU 0x001
70.189 |BASEDEF ABSABSOLUTE 00000002 frm EQU 0x002
70.190 |BASEDEF ABSABSOLUTE 00000003 fcsr EQU 0x003
70.191 |BASEDEF ABSABSOLUTE 00000C00 cycle EQU 0xC00
70.192 |BASEDEF ABSABSOLUTE 00000C01 time EQU 0xC01
70.193 |BASEDEF ABSABSOLUTE 00000C02 instret EQU 0xC02
70.194 |BASEDEF ABSABSOLUTE 00000C80 cycleh EQU 0xC80
70.195 |BASEDEF ABSABSOLUTE 00000C81 timeh EQU 0xC81
70.196 |BASEDEF ABSABSOLUTE 00000C82 instreth EQU 0xC82
71 | //
[+][-] 72 | Code TextSect // Start .text section
Macro [TEXTSECT] source location is [JAR: /framework/macros/TextSect.mac]
72.1 |TEXTSECT 000000 Code SECTION ELF_SHT_PROGBITS,ELF_SHF_ALLOC+ELF_SHF_EXECINSTR,8,".text" // Text section definition
73 | C.SUSPEND // Do not use two byte opCode extension
Use of C extension has been suspended
74 | //
[+][-] 75 | dvasmsortstring /> Entry label
Macro [ENTRY] source location is [JAR: /arch/RISCV/macros/Entry.mac]
76 | ENTRY Stack=!"" // Leaf entry, only A* and T* registers
76.1 |ENTRY EXPORT dvasmsortstring
76.2 |ENTRY 000000 dvasmsortstring DWRD 0[0]
ABSOLUTE, alignment [8], length [8], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 0000000000000000
Code [BIG ENDIAN] -> 0000000000000000
Code [DECIMAL ] -> 0
77 | // are used. No need to use a stack
78 | // or save/restore registers
[+][-] 79 | HEAPSORT a0, a1, 64, CompStr, [t0-6, a2-7] // Invoke HEAPSORT
Macro [HEAPSORT] source location is [JAR: /arch/RISCV/macros/HeapSort.mac]
79.1 |HEAPSORT //
79.2 |HEAPSORT // Registers used by macro by default or as specified by user
79.3 |HEAPSORT //
79.4 |HEAPSORT // a0 - address of buffer
79.5 |HEAPSORT // a1 - number of records in buffer
79.6 |HEAPSORT //
79.7 |HEAPSORT // t0 - end address of buffer
79.8 |HEAPSORT // t1 - end address of record being sorted
79.9 |HEAPSORT // t2 - content of record being sorted
79.10 |HEAPSORT // t3 - end offset of record being sorted
79.11 |HEAPSORT // t4 - end address of parent record when adjusting heap
79.12 |HEAPSORT // t5 - end offset of parent left child
79.13 |HEAPSORT // t6 - end address of parent left child
79.14 |HEAPSORT // a2 - content of parent left child
79.15 |HEAPSORT // a3 - content of parent right child
79.16 |HEAPSORT //
79.17 |HEAPSORT // Code to create the heap
79.18 |HEAPSORT //
79.19 |HEAPSORT 000000 139E3500 SLLI t3, 3[a1] // Get buffer Size
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 00359E13 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 11
Shift Amount.............. +03 [HEX]
Shift Amount Encoded...... 000011 [BIN] Bits [6:0]
79.20 |HEAPSORT 000004 B302AE00 ADD t0, t3, a0 // Get last record end addr
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AE02B3 [BIG ENDIAN]
Destination Register...... 5
Source 2 Register...... 10
Source 1 Register...... 28
79.21 |HEAPSORT 000008 135E1E00 SRLI t3, 1 // Get mid-record end offset
SRLI: Shift Logical Right Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001E5E13 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 28
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
79.22 |HEAPSORT 00000C 3303AE00 ADD t1, t3, a0 // Get mid-record end addr
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AE0333 [BIG ENDIAN]
Destination Register...... 6
Source 2 Register...... 10
Source 1 Register...... 28
[+][-] 79.23 |HEAPSORT WHILE Condition= ( t1 > a0 ), /> Start heap build main loop
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
79.24 |HEAPSORT RepeatCode= [!"ADDI t1, -8", />
79.25 |HEAPSORT !"ADDI t3, -8"]
79.25.1 |HEAPSORT:WHILE 000010 Asm000005 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.25.2 |HEAPSORT:WHILE __CondGen ( t1 > a0 ), true, Asm000006, Asm000007, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.25.2.1 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN BLE t1, a0, Asm000007
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
79.25.2.1.1 LE:__CONDGEN:BLE|HEAPSORT:WHILE:__CONDGEN:BLE 000010 635C650C BGE a0, t1, Asm000007
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 0C655C63 [BIG ENDIAN]
Source 1 Register...... 10
Source 2 Register...... 6
Immediate PCRel........... 0D8 [HEX]
Immediate Sect. Offset.... 000000E8 [HEX]
Immediate Bits [12:1]..... 0_0_000110_1100 [BIN] bits [12:1]
79.25.2.2 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN 000014 Asm000006 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.25.3 |HEAPSORT:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
79.26 |HEAPSORT 000014 833383FF LD t2, -8[t1] // Load record
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... FF833383 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 6
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 79.27 |HEAPSORT MV t4, t1 // Copy rec addr as parent addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.27.1 |HEAPSORT:MV 000018 930E0300 ADDI t4, 0[t1]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00030E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 6
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
79.28 |HEAPSORT 00001C 131F1E00 SLLI t5, 1[t3] // Get child end offset
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001E1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 28
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
79.29 |HEAPSORT 000020 B30FAF00 ADD t6, t5, a0 // Get child end addr
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
[+][-] 79.30 |HEAPSORT WHILE Condition= ( t6 <= t0 ), /> Get child end addr
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
79.31 |HEAPSORT RepeatCode= [!"SLLI t5, 1", /> Get new child offset
79.32 |HEAPSORT !"ADD t6, t5, a0"] // Get new child addr
79.32.1 |HEAPSORT:WHILE 000024 Asm000008 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.32.2 |HEAPSORT:WHILE __CondGen ( t6 <= t0 ), true, Asm000009, Asm000010, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.32.2.1 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN BGT t6, t0, Asm000010
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
79.32.2.1.1 LE:__CONDGEN:BGT|HEAPSORT:WHILE:__CONDGEN:BGT 000024 63CAF20B BLT t0, t6, Asm000010
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 0BF2CA63 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 31
Immediate PCRel........... 0B4 [HEX]
Immediate Sect. Offset.... 000000D8 [HEX]
Immediate Bits [12:1]..... 0_0_000101_1010 [BIN] bits [12:1]
79.32.2.2 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN 000028 Asm000009 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.32.3 |HEAPSORT:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
79.33 |HEAPSORT 000028 03B68FFF LD a2, -8[t6] // Load child
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... FF8FB603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 31
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 79.34 |HEAPSORT IF ( t6 >= t0 ), GOTO, Id= Asm000001 // Check if next child
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.34.1 |HEAPSORT:IF __CondGen ( t6 >= t0 ), false, Asm000001, Asm000011, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.34.1.1 ORT:IF:__CONDGEN|HEAPSORT:IF:__CONDGEN 00002C 63D85F06 BGE t6, t0, Asm000001
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 065FD863 [BIG ENDIAN]
Source 1 Register...... 31
Source 2 Register...... 5
Immediate PCRel........... 070 [HEX]
Immediate Sect. Offset.... 0000009C [HEX]
Immediate Bits [12:1]..... 0_0_000011_1000 [BIN] bits [12:1]
79.34.1.2 ORT:IF:__CONDGEN|HEAPSORT:IF:__CONDGEN 000030 Asm000011 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.35 |HEAPSORT 000030 83B60F00 LD a3, 0[t6] // Load child next
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 000FB683 [BIG ENDIAN]
Destination Register...... 13
Source 1 Register...... 31
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.36 |HEAPSORT CompStr a3, a2, false, Asm000001, [a4,a5,a6,a7] // Check which child is max
Macro [COMPSTR] source location is [Inline macro from line 39 to line 64 included]
[+][-] 79.36.1 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR MV a4, a3 // Copy string 1 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.36.1.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 000034 13870600 ADDI a4, 0[a3]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00068713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 13
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.36.2 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR MV a5, a2 // Copy string 2 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.36.2.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 000038 93070600 ADDI a5, 0[a2]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00060793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 12
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.36.3 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR WHILE // Start DO block
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
79.36.3.1 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 00003C Asm000012 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.36.3.2 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 00003C Asm000013 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.36.3.3 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
79.36.4 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 00003C 03480700 LBU a6, 0[a4] // Load first string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00074803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 14
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
79.36.5 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000040 83C80700 LBU a7, 0[a5] // Load second string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0007C883 [BIG ENDIAN]
Destination Register...... 17
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.36.6 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 < a7), GOTO, ID= Asm000001 // Done less than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.36.6.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 < a7), false, Asm000001, Asm000015, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.36.6.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000044 634C1805 BLT a6, a7, Asm000001
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 05184C63 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 17
Immediate PCRel........... 058 [HEX]
Immediate Sect. Offset.... 0000009C [HEX]
Immediate Bits [12:1]..... 0_0_000010_1100 [BIN] bits [12:1]
79.36.6.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000048 Asm000015 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.36.7 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 > a7), BREAK // Done if greater than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.36.7.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 > a7), false, Asm000014, Asm000016, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.36.7.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN BGT a6, a7, Asm000014
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
79.36.7.1.1.79.36.7.1.1.1 IF:__CONDGEN:BGT|HEAPSORT:COMPSTR:IF:__CONDGEN:BGT 000048 63CA0801 BLT a7, a6, Asm000014
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 0108CA63 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 16
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 0000005C [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
79.36.7.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 00004C Asm000016 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.36.8 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF ( a7 == 0 ), BREAK // Done - equal strings
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.36.8.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen ( a7 == 0 ), false, Asm000014, Asm000017, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.36.8.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 00004C 63880800 BEQ a7, 0, Asm000014
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00088863 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 0
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 0000005C [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
79.36.8.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000050 Asm000017 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.36.9 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000050 13071700 ADDI a4, 1 // Get next char address (string 1)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00170713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 14
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
79.36.10 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000054 93871700 ADDI a5, 1 // Get next char address (string 2)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00178793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 15
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 79.36.11 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
79.36.11.1 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 000058 6FF05FFE JAL Asm000013
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... FE5FF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -00001C [HEX]
Immediate Sect. Offset.... 0000003C [HEX]
Immediate Encoded......... 1_11111111_1_1111110010 [BIN] Bits [20:1]
79.36.11.2 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 00005C Asm000014 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.36.11.3 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
79.37 |HEAPSORT
[+][-] 79.38 |HEAPSORT CompStr a3, t2, true, Asm000002, [a4,a5,a6,a7] // Check if rec is max
Macro [COMPSTR] source location is [Inline macro from line 39 to line 64 included]
[+][-] 79.38.1 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR MV a4, a3 // Copy string 1 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.38.1.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 00005C 13870600 ADDI a4, 0[a3]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00068713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 13
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.38.2 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR MV a5, t2 // Copy string 2 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.38.2.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 000060 93870300 ADDI a5, 0[t2]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00038793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 7
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.38.3 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR WHILE // Start DO block
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
79.38.3.1 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 000064 Asm000018 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.38.3.2 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 000064 Asm000019 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.38.3.3 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
79.38.4 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000064 03480700 LBU a6, 0[a4] // Load first string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00074803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 14
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
79.38.5 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000068 83C80700 LBU a7, 0[a5] // Load second string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0007C883 [BIG ENDIAN]
Destination Register...... 17
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.38.6 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 < a7), GOTO, ID= Asm000002 // Done less than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.38.6.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 < a7), false, Asm000002, Asm000021, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.38.6.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 00006C 63461807 BLT a6, a7, Asm000002
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 07184663 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 17
Immediate PCRel........... 06C [HEX]
Immediate Sect. Offset.... 000000D8 [HEX]
Immediate Bits [12:1]..... 0_0_000011_0110 [BIN] bits [12:1]
79.38.6.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000070 Asm000021 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.38.7 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 > a7), BREAK // Done if greater than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.38.7.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 > a7), false, Asm000020, Asm000022, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.38.7.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN BGT a6, a7, Asm000020
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
79.38.7.1.1.79.38.7.1.1.1 IF:__CONDGEN:BGT|HEAPSORT:COMPSTR:IF:__CONDGEN:BGT 000070 63CA0801 BLT a7, a6, Asm000020
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 0108CA63 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 16
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 00000084 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
79.38.7.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000074 Asm000022 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.38.8 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF ( a7 == 0 ), GOTO, ID= Asm000002 // Equal condition with equal flag
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.38.8.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen ( a7 == 0 ), false, Asm000002, Asm000023, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.38.8.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000074 63820806 BEQ a7, 0, Asm000002
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 06088263 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 0
Immediate PCRel........... 064 [HEX]
Immediate Sect. Offset.... 000000D8 [HEX]
Immediate Bits [12:1]..... 0_0_000011_0010 [BIN] bits [12:1]
79.38.8.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000078 Asm000023 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.38.9 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000078 13071700 ADDI a4, 1 // Get next char address (string 1)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00170713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 14
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
79.38.10 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 00007C 93871700 ADDI a5, 1 // Get next char address (string 2)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00178793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 15
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 79.38.11 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
79.38.11.1 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 000080 6FF05FFE JAL Asm000019
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... FE5FF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -00001C [HEX]
Immediate Sect. Offset.... 00000064 [HEX]
Immediate Encoded......... 1_11111111_1_1111110010 [BIN] Bits [20:1]
79.38.11.2 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 000084 Asm000020 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.38.11.3 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
79.39 |HEAPSORT 000084 23BCDEFE SD a3, -8[t4] // Move next child up
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FEDEBC23 [BIG ENDIAN]
Source 2 Register...... 13
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
79.40 |HEAPSORT 000088 938E8F00 ADDI t4, 8[t6] // Next child become parent
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 008F8E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 31
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
79.41 |HEAPSORT 00008C 130F8F00 ADDI t5, 8 // Get next child offset
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 008F0F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 79.42 |HEAPSORT CONTINUE
Macro [CONTINUE] source location is [JAR: /arch/RISCV/macros/Continue.mac]
79.42.1 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 000090 131F1F00 SLLI t5, 1
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001F1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
79.42.2 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 000094 B30FAF00 ADD t6, t5, a0
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
79.42.3 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 000098 6FF0DFF8 JAL Asm000008
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... F8DFF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -000074 [HEX]
Immediate Sect. Offset.... 00000024 [HEX]
Immediate Encoded......... 1_11111111_1_1111000110 [BIN] Bits [20:1]
[+][-] 79.43 |HEAPSORT Asm000001 CompStr a2, t2, true, Asm000002, [a4,a5,a6,a7] // Check child with rec
Macro [COMPSTR] source location is [Inline macro from line 39 to line 64 included]
[+][-] 79.43.1 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR Asm000001 MV a4, a2 // Copy string 1 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.43.1.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 00009C 13070600 Asm000001 ADDI a4, 0[a2]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00060713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 12
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.43.2 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR MV a5, t2 // Copy string 2 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.43.2.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 0000A0 93870300 ADDI a5, 0[t2]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00038793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 7
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.43.3 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR WHILE // Start DO block
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
79.43.3.1 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 0000A4 Asm000024 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.43.3.2 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 0000A4 Asm000025 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.43.3.3 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
79.43.4 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 0000A4 03480700 LBU a6, 0[a4] // Load first string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00074803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 14
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
79.43.5 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 0000A8 83C80700 LBU a7, 0[a5] // Load second string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0007C883 [BIG ENDIAN]
Destination Register...... 17
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.43.6 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 < a7), GOTO, ID= Asm000002 // Done less than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.43.6.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 < a7), false, Asm000002, Asm000027, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.43.6.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 0000AC 63461803 BLT a6, a7, Asm000002
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 03184663 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 17
Immediate PCRel........... 02C [HEX]
Immediate Sect. Offset.... 000000D8 [HEX]
Immediate Bits [12:1]..... 0_0_000001_0110 [BIN] bits [12:1]
79.43.6.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 0000B0 Asm000027 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.43.7 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 > a7), BREAK // Done if greater than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.43.7.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 > a7), false, Asm000026, Asm000028, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.43.7.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN BGT a6, a7, Asm000026
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
79.43.7.1.1.79.43.7.1.1.1 IF:__CONDGEN:BGT|HEAPSORT:COMPSTR:IF:__CONDGEN:BGT 0000B0 63CA0801 BLT a7, a6, Asm000026
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 0108CA63 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 16
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 000000C4 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
79.43.7.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 0000B4 Asm000028 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.43.8 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF ( a7 == 0 ), GOTO, ID= Asm000002 // Equal condition with equal flag
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.43.8.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen ( a7 == 0 ), false, Asm000002, Asm000029, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.43.8.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 0000B4 63820802 BEQ a7, 0, Asm000002
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 02088263 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 0
Immediate PCRel........... 024 [HEX]
Immediate Sect. Offset.... 000000D8 [HEX]
Immediate Bits [12:1]..... 0_0_000001_0010 [BIN] bits [12:1]
79.43.8.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 0000B8 Asm000029 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.43.9 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 0000B8 13071700 ADDI a4, 1 // Get next char address (string 1)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00170713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 14
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
79.43.10 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 0000BC 93871700 ADDI a5, 1 // Get next char address (string 2)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00178793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 15
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 79.43.11 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
79.43.11.1 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 0000C0 6FF05FFE JAL Asm000025
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... FE5FF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -00001C [HEX]
Immediate Sect. Offset.... 000000A4 [HEX]
Immediate Encoded......... 1_11111111_1_1111110010 [BIN] Bits [20:1]
79.43.11.2 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 0000C4 Asm000026 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.43.11.3 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
79.44 |HEAPSORT 0000C4 23BCCEFE SD a2, -8[t4] // Move next child up
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FECEBC23 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
[+][-] 79.45 |HEAPSORT MV t4, t6 // Child become parent
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.45.1 |HEAPSORT:MV 0000C8 938E0F00 ADDI t4, 0[t6]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 000F8E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 31
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.46 |HEAPSORT ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
79.46.1 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 0000CC 131F1F00 SLLI t5, 1
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001F1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
79.46.2 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 0000D0 B30FAF00 ADD t6, t5, a0
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
[+][-] 79.46.3 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE __CondGen ( t6 <= t0 ), false, Asm000009, Asm000010, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.46.3.1 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN BLE t6, t0, Asm000009
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
79.46.3.1.1 LE:__CONDGEN:BLE|HEAPSORT:ENDWHILE:__CONDGEN:BLE 0000D4 E3DAF2F5 BGE t0, t6, Asm000009
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... F5F2DAE3 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 31
Immediate PCRel........... -AC [HEX]
Immediate Sect. Offset.... 00000028 [HEX]
Immediate Bits [12:1]..... 1_1_111010_1010 [BIN] bits [12:1]
79.46.3.2 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN 0000D8 Asm000010 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.46.4 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
79.47 |HEAPSORT 0000D8 23BC7EFE Asm000002 SD t2, -8[t4]
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FE7EBC23 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
[+][-] 79.48 |HEAPSORT ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
79.48.1 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 0000DC 130383FF ADDI t1, -8
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF830313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 6
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
79.48.2 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 0000E0 130E8EFF ADDI t3, -8
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF8E0E13 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 28
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 79.48.3 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE __CondGen ( t1 > a0 ), false, Asm000006, Asm000007, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.48.3.1 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN BGT t1, a0, Asm000006
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
79.48.3.1.1 LE:__CONDGEN:BGT|HEAPSORT:ENDWHILE:__CONDGEN:BGT 0000E4 E34865F2 BLT a0, t1, Asm000006
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... F26548E3 [BIG ENDIAN]
Source 1 Register...... 10
Source 2 Register...... 6
Immediate PCRel........... -D0 [HEX]
Immediate Sect. Offset.... 00000014 [HEX]
Immediate Bits [12:1]..... 1_1_111001_1000 [BIN] bits [12:1]
79.48.3.2 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN 0000E8 Asm000007 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.48.4 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
79.49 |HEAPSORT //
79.50 |HEAPSORT // Code to sort
79.51 |HEAPSORT //
79.52 |HEAPSORT 0000E8 938282FF ADDI t0, -8 // Reduce heap Size by one
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF828293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 79.53 |HEAPSORT WHILE Condition= ( t0 > a0 ), /> Start sort main loop
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
79.54 |HEAPSORT RepeatCode= [!"ADDI t0,-8"]
79.54.1 |HEAPSORT:WHILE 0000EC Asm000030 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.54.2 |HEAPSORT:WHILE __CondGen ( t0 > a0 ), true, Asm000031, Asm000032, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.54.2.1 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN BLE t0, a0, Asm000032
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
79.54.2.1.1 LE:__CONDGEN:BLE|HEAPSORT:WHILE:__CONDGEN:BLE 0000EC 6352550E BGE a0, t0, Asm000032
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 0E555263 [BIG ENDIAN]
Source 1 Register...... 10
Source 2 Register...... 5
Immediate PCRel........... 0E4 [HEX]
Immediate Sect. Offset.... 000001D0 [HEX]
Immediate Bits [12:1]..... 0_0_000111_0010 [BIN] bits [12:1]
79.54.2.2 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN 0000F0 Asm000031 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.54.3 |HEAPSORT:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
79.55 |HEAPSORT 0000F0 130E8000 ADDI t3, 8[0] // Get starting record end offset
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00800E13 [BIG ENDIAN]
Destination Register...... 28
Source 1 Register...... 0
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
79.56 |HEAPSORT 0000F4 13038500 ADDI t1, 8[a0] // Get starting record end addr
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00850313 [BIG ENDIAN]
Destination Register...... 6
Source 1 Register...... 10
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
79.57 |HEAPSORT 0000F8 83B30200 LD t2, 0[t0] // Load record
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0002B383 [BIG ENDIAN]
Destination Register...... 7
Source 1 Register...... 5
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
79.58 |HEAPSORT 0000FC 03360500 LD a2, 0[a0] // Get firt record in heap - last in sort order
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00053603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 10
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
79.59 |HEAPSORT 000100 23B0C200 SD a2, 0[t0] // Store at the end of the heap
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... 00C2B023 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 5
Immediate Displacement.... +000 [HEX]
Immediate Encoded......... 0000000_00000 [BIN] Bits [11:0]
[+][-] 79.60 |HEAPSORT MV t4, t1 // Copy rec addr as parent addr
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.60.1 |HEAPSORT:MV 000104 930E0300 ADDI t4, 0[t1]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00030E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 6
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
79.61 |HEAPSORT 000108 131F1E00 SLLI t5, 1[t3] // Get child end offset
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001E1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 28
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
79.62 |HEAPSORT 00010C B30FAF00 ADD t6, t5, a0 // Get child end addr
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
[+][-] 79.63 |HEAPSORT WHILE Condition= ( t6 <= t0 ), /> Get child end addr
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
79.64 |HEAPSORT RepeatCode= [!"SLLI t5, 1", /> Get new child offset
79.65 |HEAPSORT !"ADD t6, t5, a0"] // Get new child addr
79.65.1 |HEAPSORT:WHILE 000110 Asm000033 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.65.2 |HEAPSORT:WHILE __CondGen ( t6 <= t0 ), true, Asm000034, Asm000035, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.65.2.1 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN BGT t6, t0, Asm000035
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
79.65.2.1.1 LE:__CONDGEN:BGT|HEAPSORT:WHILE:__CONDGEN:BGT 000110 63CAF20B BLT t0, t6, Asm000035
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 0BF2CA63 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 31
Immediate PCRel........... 0B4 [HEX]
Immediate Sect. Offset.... 000001C4 [HEX]
Immediate Bits [12:1]..... 0_0_000101_1010 [BIN] bits [12:1]
79.65.2.2 :WHILE:__CONDGEN|HEAPSORT:WHILE:__CONDGEN 000114 Asm000034 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.65.3 |HEAPSORT:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
79.66 |HEAPSORT 000114 03B68FFF LD a2, -8[t6] // Load child
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... FF8FB603 [BIG ENDIAN]
Destination Register...... 12
Source 1 Register...... 31
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 79.67 |HEAPSORT IF ( t6 >= t0 ), GOTO, Id= Asm000003 // Check if next child
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.67.1 |HEAPSORT:IF __CondGen ( t6 >= t0 ), false, Asm000003, Asm000036, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.67.1.1 ORT:IF:__CONDGEN|HEAPSORT:IF:__CONDGEN 000118 63D85F06 BGE t6, t0, Asm000003
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... 065FD863 [BIG ENDIAN]
Source 1 Register...... 31
Source 2 Register...... 5
Immediate PCRel........... 070 [HEX]
Immediate Sect. Offset.... 00000188 [HEX]
Immediate Bits [12:1]..... 0_0_000011_1000 [BIN] bits [12:1]
79.67.1.2 ORT:IF:__CONDGEN|HEAPSORT:IF:__CONDGEN 00011C Asm000036 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.68 |HEAPSORT 00011C 83B60F00 LD a3, 0[t6] // Load child next
LD: Load sign extended word into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 000FB683 [BIG ENDIAN]
Destination Register...... 13
Source 1 Register...... 31
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.69 |HEAPSORT CompStr a3, a2, false, Asm000003, [a4,a5,a6,a7] // Check which child is max
Macro [COMPSTR] source location is [Inline macro from line 39 to line 64 included]
[+][-] 79.69.1 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR MV a4, a3 // Copy string 1 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.69.1.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 000120 13870600 ADDI a4, 0[a3]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00068713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 13
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.69.2 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR MV a5, a2 // Copy string 2 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.69.2.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 000124 93070600 ADDI a5, 0[a2]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00060793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 12
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.69.3 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR WHILE // Start DO block
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
79.69.3.1 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 000128 Asm000037 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.69.3.2 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 000128 Asm000038 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.69.3.3 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
79.69.4 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000128 03480700 LBU a6, 0[a4] // Load first string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00074803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 14
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
79.69.5 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 00012C 83C80700 LBU a7, 0[a5] // Load second string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0007C883 [BIG ENDIAN]
Destination Register...... 17
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.69.6 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 < a7), GOTO, ID= Asm000003 // Done less than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.69.6.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 < a7), false, Asm000003, Asm000040, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.69.6.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000130 634C1805 BLT a6, a7, Asm000003
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 05184C63 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 17
Immediate PCRel........... 058 [HEX]
Immediate Sect. Offset.... 00000188 [HEX]
Immediate Bits [12:1]..... 0_0_000010_1100 [BIN] bits [12:1]
79.69.6.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000134 Asm000040 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.69.7 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 > a7), BREAK // Done if greater than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.69.7.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 > a7), false, Asm000039, Asm000041, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.69.7.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN BGT a6, a7, Asm000039
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
79.69.7.1.1.79.69.7.1.1.1 IF:__CONDGEN:BGT|HEAPSORT:COMPSTR:IF:__CONDGEN:BGT 000134 63CA0801 BLT a7, a6, Asm000039
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 0108CA63 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 16
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 00000148 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
79.69.7.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000138 Asm000041 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.69.8 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF ( a7 == 0 ), BREAK // Done - equal strings
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.69.8.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen ( a7 == 0 ), false, Asm000039, Asm000042, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.69.8.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000138 63880800 BEQ a7, 0, Asm000039
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 00088863 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 0
Immediate PCRel........... 010 [HEX]
Immediate Sect. Offset.... 00000148 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1000 [BIN] bits [12:1]
79.69.8.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 00013C Asm000042 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.69.9 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 00013C 13071700 ADDI a4, 1 // Get next char address (string 1)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00170713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 14
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
79.69.10 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000140 93871700 ADDI a5, 1 // Get next char address (string 2)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00178793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 15
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 79.69.11 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
79.69.11.1 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 000144 6FF05FFE JAL Asm000038
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... FE5FF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -00001C [HEX]
Immediate Sect. Offset.... 00000128 [HEX]
Immediate Encoded......... 1_11111111_1_1111110010 [BIN] Bits [20:1]
79.69.11.2 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 000148 Asm000039 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.69.11.3 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 79.70 |HEAPSORT CompStr a3, t2, true, Asm000004, [a4,a5,a6,a7] // Check if rec is max
Macro [COMPSTR] source location is [Inline macro from line 39 to line 64 included]
[+][-] 79.70.1 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR MV a4, a3 // Copy string 1 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.70.1.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 000148 13870600 ADDI a4, 0[a3]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00068713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 13
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.70.2 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR MV a5, t2 // Copy string 2 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.70.2.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 00014C 93870300 ADDI a5, 0[t2]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00038793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 7
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.70.3 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR WHILE // Start DO block
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
79.70.3.1 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 000150 Asm000043 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.70.3.2 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 000150 Asm000044 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.70.3.3 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
79.70.4 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000150 03480700 LBU a6, 0[a4] // Load first string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00074803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 14
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
79.70.5 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000154 83C80700 LBU a7, 0[a5] // Load second string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0007C883 [BIG ENDIAN]
Destination Register...... 17
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.70.6 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 < a7), GOTO, ID= Asm000004 // Done less than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.70.6.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 < a7), false, Asm000004, Asm000046, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.70.6.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000158 63461807 BLT a6, a7, Asm000004
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 07184663 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 17
Immediate PCRel........... 06C [HEX]
Immediate Sect. Offset.... 000001C4 [HEX]
Immediate Bits [12:1]..... 0_0_000011_0110 [BIN] bits [12:1]
79.70.6.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 00015C Asm000046 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.70.7 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 > a7), BREAK // Done if greater than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.70.7.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 > a7), false, Asm000045, Asm000047, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.70.7.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN BGT a6, a7, Asm000045
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
79.70.7.1.1.79.70.7.1.1.1 IF:__CONDGEN:BGT|HEAPSORT:COMPSTR:IF:__CONDGEN:BGT 00015C 63CA0801 BLT a7, a6, Asm000045
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 0108CA63 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 16
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 00000170 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
79.70.7.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000160 Asm000047 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.70.8 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF ( a7 == 0 ), GOTO, ID= Asm000004 // Equal condition with equal flag
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.70.8.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen ( a7 == 0 ), false, Asm000004, Asm000048, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.70.8.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000160 63820806 BEQ a7, 0, Asm000004
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 06088263 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 0
Immediate PCRel........... 064 [HEX]
Immediate Sect. Offset.... 000001C4 [HEX]
Immediate Bits [12:1]..... 0_0_000011_0010 [BIN] bits [12:1]
79.70.8.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000164 Asm000048 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.70.9 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000164 13071700 ADDI a4, 1 // Get next char address (string 1)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00170713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 14
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
79.70.10 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000168 93871700 ADDI a5, 1 // Get next char address (string 2)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00178793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 15
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 79.70.11 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
79.70.11.1 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 00016C 6FF05FFE JAL Asm000044
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... FE5FF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -00001C [HEX]
Immediate Sect. Offset.... 00000150 [HEX]
Immediate Encoded......... 1_11111111_1_1111110010 [BIN] Bits [20:1]
79.70.11.2 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 000170 Asm000045 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.70.11.3 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
79.71 |HEAPSORT 000170 23BCDEFE SD a3, -8[t4] // Move next child up
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FEDEBC23 [BIG ENDIAN]
Source 2 Register...... 13
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
79.72 |HEAPSORT 000174 938E8F00 ADDI t4, 8[t6] // Next child become parent
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 008F8E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 31
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
79.73 |HEAPSORT 000178 130F8F00 ADDI t5, 8 // Get next child offset
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 008F0F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Immediate................. +008 [HEX]
Immediate Encoded......... 000000001000 [BIN] Bits [11:0]
[+][-] 79.74 |HEAPSORT CONTINUE
Macro [CONTINUE] source location is [JAR: /arch/RISCV/macros/Continue.mac]
79.74.1 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 00017C 131F1F00 SLLI t5, 1
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001F1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
79.74.2 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 000180 B30FAF00 ADD t6, t5, a0
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
79.74.3 EAPSORT:CONTINUE|HEAPSORT:CONTINUE 000184 6FF0DFF8 JAL Asm000033
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... F8DFF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -000074 [HEX]
Immediate Sect. Offset.... 00000110 [HEX]
Immediate Encoded......... 1_11111111_1_1111000110 [BIN] Bits [20:1]
[+][-] 79.75 |HEAPSORT Asm000003 CompStr a2, t2, true, Asm000004, [a4,a5,a6,a7] // Check child with rec
Macro [COMPSTR] source location is [Inline macro from line 39 to line 64 included]
[+][-] 79.75.1 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR Asm000003 MV a4, a2 // Copy string 1 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.75.1.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 000188 13070600 Asm000003 ADDI a4, 0[a2]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00060713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 12
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.75.2 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR MV a5, t2 // Copy string 2 address
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.75.2.1 PSORT:COMPSTR:MV|HEAPSORT:COMPSTR:MV 00018C 93870300 ADDI a5, 0[t2]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00038793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 7
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.75.3 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR WHILE // Start DO block
Macro [WHILE] source location is [JAR: /arch/RISCV/macros/While.mac]
79.75.3.1 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 000190 Asm000049 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.75.3.2 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE 000190 Asm000050 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.75.3.3 RT:COMPSTR:WHILE|HEAPSORT:COMPSTR:WHILE INDENTIN
Macro [INDENTIN] source location is [JAR: /framework/macros/IndentIn.mac]
79.75.4 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000190 03480700 LBU a6, 0[a4] // Load first string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 00074803 [BIG ENDIAN]
Destination Register...... 16
Source 1 Register...... 14
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
79.75.5 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 000194 83C80700 LBU a7, 0[a5] // Load second string byte
LBU: Load zero extended byte into RegD at Reg1 relative sign extended Immediate
Machine Instruction....... 0007C883 [BIG ENDIAN]
Destination Register...... 17
Source 1 Register...... 15
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.75.6 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 < a7), GOTO, ID= Asm000004 // Done less than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.75.6.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 < a7), false, Asm000004, Asm000052, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.75.6.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 000198 63461803 BLT a6, a7, Asm000004
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 03184663 [BIG ENDIAN]
Source 1 Register...... 16
Source 2 Register...... 17
Immediate PCRel........... 02C [HEX]
Immediate Sect. Offset.... 000001C4 [HEX]
Immediate Bits [12:1]..... 0_0_000001_0110 [BIN] bits [12:1]
79.75.6.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 00019C Asm000052 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.75.7 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF (a6 > a7), BREAK // Done if greater than
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.75.7.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen (a6 > a7), false, Asm000051, Asm000053, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.75.7.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN BGT a6, a7, Asm000051
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
79.75.7.1.1.79.75.7.1.1.1 IF:__CONDGEN:BGT|HEAPSORT:COMPSTR:IF:__CONDGEN:BGT 00019C 63CA0801 BLT a7, a6, Asm000051
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... 0108CA63 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 16
Immediate PCRel........... 014 [HEX]
Immediate Sect. Offset.... 000001B0 [HEX]
Immediate Bits [12:1]..... 0_0_000000_1010 [BIN] bits [12:1]
79.75.7.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 0001A0 Asm000053 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
[+][-] 79.75.8 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR IF ( a7 == 0 ), GOTO, ID= Asm000004 // Equal condition with equal flag
Macro [IF] source location is [JAR: /arch/RISCV/macros/If.mac]
[+][-] 79.75.8.1 PSORT:COMPSTR:IF|HEAPSORT:COMPSTR:IF __CondGen ( a7 == 0 ), false, Asm000004, Asm000054, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
79.75.8.1.1 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 0001A0 63820802 BEQ a7, 0, Asm000004
BEQ: Branch to PC relative signed extended Immediate multiplied by 2 if signed Reg1 == Reg2 (signed)
Machine Instruction....... 02088263 [BIG ENDIAN]
Source 1 Register...... 17
Source 2 Register...... 0
Immediate PCRel........... 024 [HEX]
Immediate Sect. Offset.... 000001C4 [HEX]
Immediate Bits [12:1]..... 0_0_000001_0010 [BIN] bits [12:1]
79.75.8.1.2 STR:IF:__CONDGEN|HEAPSORT:COMPSTR:IF:__CONDGEN 0001A4 Asm000054 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.75.9 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 0001A4 13071700 ADDI a4, 1 // Get next char address (string 1)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00170713 [BIG ENDIAN]
Destination Register...... 14
Source 1 Register...... 14
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
79.75.10 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR 0001A8 93871700 ADDI a5, 1 // Get next char address (string 2)
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 00178793 [BIG ENDIAN]
Destination Register...... 15
Source 1 Register...... 15
Immediate................. +001 [HEX]
Immediate Encoded......... 000000000001 [BIN] Bits [11:0]
[+][-] 79.75.11 HEAPSORT:COMPSTR|HEAPSORT:COMPSTR ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
79.75.11.1 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 0001AC 6FF05FFE JAL Asm000050
JAL: Jump to PC relative sign extended Immediate shifted left by 1, and store link address in RegD
Machine Instruction....... FE5FF06F [BIG ENDIAN]
Destination Register...... 0
Immediate PCRel........... -00001C [HEX]
Immediate Sect. Offset.... 00000190 [HEX]
Immediate Encoded......... 1_11111111_1_1111110010 [BIN] Bits [20:1]
79.75.11.2 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE 0001B0 Asm000051 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.75.11.3 COMPSTR:ENDWHILE|HEAPSORT:COMPSTR:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
79.76 |HEAPSORT 0001B0 23BCCEFE SD a2, -8[t4] // Move next child up
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FECEBC23 [BIG ENDIAN]
Source 2 Register...... 12
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
[+][-] 79.77 |HEAPSORT MV t4, t6 // Child become parent
Macro [MV] source location is [JAR: /arch/RISCV/macros/Mv.mac]
79.77.1 |HEAPSORT:MV 0001B4 938E0F00 ADDI t4, 0[t6]
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... 000F8E93 [BIG ENDIAN]
Destination Register...... 29
Source 1 Register...... 31
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
[+][-] 79.78 |HEAPSORT ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
79.78.1 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 0001B8 131F1F00 SLLI t5, 1
SLLI: Shift Logical Left Reg1 by the Shift Amount and store result in RegD
Machine Instruction....... 001F1F13 [BIG ENDIAN]
Destination Register...... 30
Source 1 Register...... 30
Shift Amount.............. +01 [HEX]
Shift Amount Encoded...... 000001 [BIN] Bits [6:0]
79.78.2 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 0001BC B30FAF00 ADD t6, t5, a0
ADD: Add Reg2 to Reg1 and store result in RegD
Machine Instruction....... 00AF0FB3 [BIG ENDIAN]
Destination Register...... 31
Source 2 Register...... 10
Source 1 Register...... 30
[+][-] 79.78.3 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE __CondGen ( t6 <= t0 ), false, Asm000034, Asm000035, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.78.3.1 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN BLE t6, t0, Asm000034
Macro [BLE] source location is [JAR: /arch/RISCV/macros/Ble.mac]
79.78.3.1.1 LE:__CONDGEN:BLE|HEAPSORT:ENDWHILE:__CONDGEN:BLE 0001C0 E3DAF2F5 BGE t0, t6, Asm000034
BGE: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 >= Reg2 (signed)
Machine Instruction....... F5F2DAE3 [BIG ENDIAN]
Source 1 Register...... 5
Source 2 Register...... 31
Immediate PCRel........... -AC [HEX]
Immediate Sect. Offset.... 00000114 [HEX]
Immediate Bits [12:1]..... 1_1_111010_1010 [BIN] bits [12:1]
79.78.3.2 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN 0001C4 Asm000035 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.78.4 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
79.79 |HEAPSORT 0001C4 23BC7EFE Asm000004 SD t2, -8[t4] // Save record in current child
SD: Store Reg2 double word into Reg1 relative sign extended Immediate memory address
Machine Instruction....... FE7EBC23 [BIG ENDIAN]
Source 2 Register...... 7
Src. 1/Base Register...... 29
Immediate Displacement.... -008 [HEX]
Immediate Encoded......... 1111111_11000 [BIN] Bits [11:0]
[+][-] 79.80 |HEAPSORT ENDWHILE
Macro [ENDWHILE] source location is [JAR: /arch/RISCV/macros/EndWhile.mac]
79.80.1 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE 0001C8 938282FF ADDI t0,-8
ADDI: Add sign extended Immediate to Reg1 and store result into RegD
Machine Instruction....... FF828293 [BIG ENDIAN]
Destination Register...... 5
Source 1 Register...... 5
Immediate................. -008 [HEX]
Immediate Encoded......... 111111111000 [BIN] Bits [11:0]
[+][-] 79.80.2 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE __CondGen ( t0 > a0 ), false, Asm000031, Asm000032, WReg= , false
Macro [__CONDGEN] source location is [JAR: /arch/RISCV/macros/__CondGen.mac]
[+][-] 79.80.2.1 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN BGT t0, a0, Asm000031
Macro [BGT] source location is [JAR: /arch/RISCV/macros/Bgt.mac]
79.80.2.1.1 LE:__CONDGEN:BGT|HEAPSORT:ENDWHILE:__CONDGEN:BGT 0001CC E34255F2 BLT a0, t0, Asm000031
BLT: Branch to PC relative signed extended Immediate multiplied by 2 if Reg1 < Reg2 (signed)
Machine Instruction....... F25542E3 [BIG ENDIAN]
Source 1 Register...... 10
Source 2 Register...... 5
Immediate PCRel........... -DC [HEX]
Immediate Sect. Offset.... 000000F0 [HEX]
Immediate Bits [12:1]..... 1_1_111001_0010 [BIN] bits [12:1]
79.80.2.2 DWHILE:__CONDGEN|HEAPSORT:ENDWHILE:__CONDGEN 0001D0 Asm000032 BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
79.80.3 EAPSORT:ENDWHILE|HEAPSORT:ENDWHILE INDENTOUT
Macro [INDENTOUT] source location is [JAR: /framework/macros/IndentOut.mac]
[+][-] 80 | Exit EXIT // Return to caller
Macro [EXIT] source location is [JAR: /arch/RISCV/macros/Exit.mac]
80.1 |EXIT 0001D0 Exit BYTE 0[0]
ABSOLUTE, alignment [1], length [1], replication [0], endianness LITTLE
Code [LITTLE ENDIAN] -> 00
Code [DECIMAL ] -> 0
80.2 |EXIT 0001D0 67800000 JALR 0, 0[ra] // Return to caller
JALR: Jump to ( Reg1 + immediate ) address, and store link address in RegD
Machine Instruction....... 00008067 [BIG ENDIAN]
Destination Register...... 0
Source 1 Register...... 1
Immediate................. +000 [HEX]
Immediate Encoded......... 000000000000 [BIN] Bits [11:0]
81 | //
82 | END
Code SECTION 00008 000001D4 .text PROGBITS ALLOC+EXECUTE
[+][-] A0 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 70.84
Referenced in Statement: 79.20
Referenced in Statement: 79.22
Referenced in Statement: 79.25.2.1.1
Referenced in Statement: 79.29
Referenced in Statement: 79.42.2
Referenced in Statement: 79.46.2
Referenced in Statement: 79.48.3.1.1
Referenced in Statement: 79.54.2.1.1
Referenced in Statement: 79.56
Referenced in Statement: 79.58
Referenced in Statement: 79.62
Referenced in Statement: 79.74.2
Referenced in Statement: 79.78.2
Referenced in Statement: 79.80.2.1.1
[+][-] A1 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 70.85
Referenced in Statement: 79.19
[+][-] A2 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 70.86
Referenced in Statement: 79.33
Referenced in Statement: 79.36.2.1
Referenced in Statement: 79.43.1.1
Referenced in Statement: 79.44
Referenced in Statement: 79.58
Referenced in Statement: 79.59
Referenced in Statement: 79.66
Referenced in Statement: 79.69.2.1
Referenced in Statement: 79.75.1.1
Referenced in Statement: 79.76
[+][-] A3 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 70.87
Referenced in Statement: 79.35
Referenced in Statement: 79.36.1.1
Referenced in Statement: 79.38.1.1
Referenced in Statement: 79.39
Referenced in Statement: 79.68
Referenced in Statement: 79.69.1.1
Referenced in Statement: 79.70.1.1
Referenced in Statement: 79.71
[+][-] A4 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 70.88
Referenced in Statement: 79.36.1.1
Referenced in Statement: 79.36.4
Referenced in Statement: 79.36.9
Referenced in Statement: 79.38.1.1
Referenced in Statement: 79.38.4
Referenced in Statement: 79.38.9
Referenced in Statement: 79.43.1.1
Referenced in Statement: 79.43.4
Referenced in Statement: 79.43.9
Referenced in Statement: 79.69.1.1
Referenced in Statement: 79.69.4
Referenced in Statement: 79.69.9
Referenced in Statement: 79.70.1.1
Referenced in Statement: 79.70.4
Referenced in Statement: 79.70.9
Referenced in Statement: 79.75.1.1
Referenced in Statement: 79.75.4
Referenced in Statement: 79.75.9
[+][-] A5 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 70.89
Referenced in Statement: 79.36.10
Referenced in Statement: 79.36.2.1
Referenced in Statement: 79.36.5
Referenced in Statement: 79.38.10
Referenced in Statement: 79.38.2.1
Referenced in Statement: 79.38.5
Referenced in Statement: 79.43.10
Referenced in Statement: 79.43.2.1
Referenced in Statement: 79.43.5
Referenced in Statement: 79.69.10
Referenced in Statement: 79.69.2.1
Referenced in Statement: 79.69.5
Referenced in Statement: 79.70.10
Referenced in Statement: 79.70.2.1
Referenced in Statement: 79.70.5
Referenced in Statement: 79.75.10
Referenced in Statement: 79.75.2.1
Referenced in Statement: 79.75.5
[+][-] A6 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 70.90
Referenced in Statement: 79.36.4
Referenced in Statement: 79.36.6.1.1
Referenced in Statement: 79.36.7.1.1.1
Referenced in Statement: 79.38.4
Referenced in Statement: 79.38.6.1.1
Referenced in Statement: 79.38.7.1.1.1
Referenced in Statement: 79.43.4
Referenced in Statement: 79.43.6.1.1
Referenced in Statement: 79.43.7.1.1.1
Referenced in Statement: 79.69.4
Referenced in Statement: 79.69.6.1.1
Referenced in Statement: 79.69.7.1.1.1
Referenced in Statement: 79.70.4
Referenced in Statement: 79.70.6.1.1
Referenced in Statement: 79.70.7.1.1.1
Referenced in Statement: 79.75.4
Referenced in Statement: 79.75.6.1.1
Referenced in Statement: 79.75.7.1.1.1
[+][-] A7 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 70.91
Referenced in Statement: 79.36.5
Referenced in Statement: 79.36.6.1.1
Referenced in Statement: 79.36.7.1.1.1
Referenced in Statement: 79.36.8.1.1
Referenced in Statement: 79.38.5
Referenced in Statement: 79.38.6.1.1
Referenced in Statement: 79.38.7.1.1.1
Referenced in Statement: 79.38.8.1.1
Referenced in Statement: 79.43.5
Referenced in Statement: 79.43.6.1.1
Referenced in Statement: 79.43.7.1.1.1
Referenced in Statement: 79.43.8.1.1
Referenced in Statement: 79.69.5
Referenced in Statement: 79.69.6.1.1
Referenced in Statement: 79.69.7.1.1.1
Referenced in Statement: 79.69.8.1.1
Referenced in Statement: 79.70.5
Referenced in Statement: 79.70.6.1.1
Referenced in Statement: 79.70.7.1.1.1
Referenced in Statement: 79.70.8.1.1
Referenced in Statement: 79.75.5
Referenced in Statement: 79.75.6.1.1
Referenced in Statement: 79.75.7.1.1.1
Referenced in Statement: 79.75.8.1.1
[+][-] ASM000001 OFFSET [Code] 00002 00004 00001 000004 0000009C
Defined in Statement: 79.43.1.1
Referenced in Statement: 79.34.1.1
Referenced in Statement: 79.36.6.1.1
[+][-] ASM000002 OFFSET [Code] 00002 00004 00001 000004 000000D8
Defined in Statement: 79.47
Referenced in Statement: 79.38.6.1.1
Referenced in Statement: 79.38.8.1.1
Referenced in Statement: 79.43.6.1.1
Referenced in Statement: 79.43.8.1.1
[+][-] ASM000003 OFFSET [Code] 00002 00004 00001 000004 00000188
Defined in Statement: 79.75.1.1
Referenced in Statement: 79.67.1.1
Referenced in Statement: 79.69.6.1.1
[+][-] ASM000004 OFFSET [Code] 00002 00004 00001 000004 000001C4
Defined in Statement: 79.79
Referenced in Statement: 79.70.6.1.1
Referenced in Statement: 79.70.8.1.1
Referenced in Statement: 79.75.6.1.1
Referenced in Statement: 79.75.8.1.1
[+][-] ASM000005 OFFSET [Code] 00001 00001 00000 000000 00000010
Defined in Statement: 79.25.1
[+][-] ASM000006 OFFSET [Code] 00001 00001 00000 000000 00000014
Defined in Statement: 79.25.2.2
Referenced in Statement: 79.48.3.1.1
[+][-] ASM000007 OFFSET [Code] 00001 00001 00000 000000 000000E8
Defined in Statement: 79.48.3.2
Referenced in Statement: 79.25.2.1.1
[+][-] ASM000008 OFFSET [Code] 00001 00001 00000 000000 00000024
Defined in Statement: 79.32.1
Referenced in Statement: 79.42.3
[+][-] ASM000009 OFFSET [Code] 00001 00001 00000 000000 00000028
Defined in Statement: 79.32.2.2
Referenced in Statement: 79.46.3.1.1
[+][-] ASM000010 OFFSET [Code] 00001 00001 00000 000000 000000D8
Defined in Statement: 79.46.3.2
Referenced in Statement: 79.32.2.1.1
[+][-] ASM000011 OFFSET [Code] 00001 00001 00000 000000 00000030
Defined in Statement: 79.34.1.2
[+][-] ASM000012 OFFSET [Code] 00001 00001 00000 000000 0000003C
Defined in Statement: 79.36.3.1
[+][-] ASM000013 OFFSET [Code] 00001 00001 00000 000000 0000003C
Defined in Statement: 79.36.3.2
Referenced in Statement: 79.36.11.1
[+][-] ASM000014 OFFSET [Code] 00001 00001 00000 000000 0000005C
Defined in Statement: 79.36.11.2
Referenced in Statement: 79.36.7.1.1.1
Referenced in Statement: 79.36.8.1.1
[+][-] ASM000015 OFFSET [Code] 00001 00001 00000 000000 00000048
Defined in Statement: 79.36.6.1.2
[+][-] ASM000016 OFFSET [Code] 00001 00001 00000 000000 0000004C
Defined in Statement: 79.36.7.1.2
[+][-] ASM000017 OFFSET [Code] 00001 00001 00000 000000 00000050
Defined in Statement: 79.36.8.1.2
[+][-] ASM000018 OFFSET [Code] 00001 00001 00000 000000 00000064
Defined in Statement: 79.38.3.1
[+][-] ASM000019 OFFSET [Code] 00001 00001 00000 000000 00000064
Defined in Statement: 79.38.3.2
Referenced in Statement: 79.38.11.1
[+][-] ASM000020 OFFSET [Code] 00001 00001 00000 000000 00000084
Defined in Statement: 79.38.11.2
Referenced in Statement: 79.38.7.1.1.1
[+][-] ASM000021 OFFSET [Code] 00001 00001 00000 000000 00000070
Defined in Statement: 79.38.6.1.2
[+][-] ASM000022 OFFSET [Code] 00001 00001 00000 000000 00000074
Defined in Statement: 79.38.7.1.2
[+][-] ASM000023 OFFSET [Code] 00001 00001 00000 000000 00000078
Defined in Statement: 79.38.8.1.2
[+][-] ASM000024 OFFSET [Code] 00001 00001 00000 000000 000000A4
Defined in Statement: 79.43.3.1
[+][-] ASM000025 OFFSET [Code] 00001 00001 00000 000000 000000A4
Defined in Statement: 79.43.3.2
Referenced in Statement: 79.43.11.1
[+][-] ASM000026 OFFSET [Code] 00001 00001 00000 000000 000000C4
Defined in Statement: 79.43.11.2
Referenced in Statement: 79.43.7.1.1.1
[+][-] ASM000027 OFFSET [Code] 00001 00001 00000 000000 000000B0
Defined in Statement: 79.43.6.1.2
[+][-] ASM000028 OFFSET [Code] 00001 00001 00000 000000 000000B4
Defined in Statement: 79.43.7.1.2
[+][-] ASM000029 OFFSET [Code] 00001 00001 00000 000000 000000B8
Defined in Statement: 79.43.8.1.2
[+][-] ASM000030 OFFSET [Code] 00001 00001 00000 000000 000000EC
Defined in Statement: 79.54.1
[+][-] ASM000031 OFFSET [Code] 00001 00001 00000 000000 000000F0
Defined in Statement: 79.54.2.2
Referenced in Statement: 79.80.2.1.1
[+][-] ASM000032 OFFSET [Code] 00001 00001 00000 000000 000001D0
Defined in Statement: 79.80.2.2
Referenced in Statement: 79.54.2.1.1
[+][-] ASM000033 OFFSET [Code] 00001 00001 00000 000000 00000110
Defined in Statement: 79.65.1
Referenced in Statement: 79.74.3
[+][-] ASM000034 OFFSET [Code] 00001 00001 00000 000000 00000114
Defined in Statement: 79.65.2.2
Referenced in Statement: 79.78.3.1.1
[+][-] ASM000035 OFFSET [Code] 00001 00001 00000 000000 000001C4
Defined in Statement: 79.78.3.2
Referenced in Statement: 79.65.2.1.1
[+][-] ASM000036 OFFSET [Code] 00001 00001 00000 000000 0000011C
Defined in Statement: 79.67.1.2
[+][-] ASM000037 OFFSET [Code] 00001 00001 00000 000000 00000128
Defined in Statement: 79.69.3.1
[+][-] ASM000038 OFFSET [Code] 00001 00001 00000 000000 00000128
Defined in Statement: 79.69.3.2
Referenced in Statement: 79.69.11.1
[+][-] ASM000039 OFFSET [Code] 00001 00001 00000 000000 00000148
Defined in Statement: 79.69.11.2
Referenced in Statement: 79.69.7.1.1.1
Referenced in Statement: 79.69.8.1.1
[+][-] ASM000040 OFFSET [Code] 00001 00001 00000 000000 00000134
Defined in Statement: 79.69.6.1.2
[+][-] ASM000041 OFFSET [Code] 00001 00001 00000 000000 00000138
Defined in Statement: 79.69.7.1.2
[+][-] ASM000042 OFFSET [Code] 00001 00001 00000 000000 0000013C
Defined in Statement: 79.69.8.1.2
[+][-] ASM000043 OFFSET [Code] 00001 00001 00000 000000 00000150
Defined in Statement: 79.70.3.1
[+][-] ASM000044 OFFSET [Code] 00001 00001 00000 000000 00000150
Defined in Statement: 79.70.3.2
Referenced in Statement: 79.70.11.1
[+][-] ASM000045 OFFSET [Code] 00001 00001 00000 000000 00000170
Defined in Statement: 79.70.11.2
Referenced in Statement: 79.70.7.1.1.1
[+][-] ASM000046 OFFSET [Code] 00001 00001 00000 000000 0000015C
Defined in Statement: 79.70.6.1.2
[+][-] ASM000047 OFFSET [Code] 00001 00001 00000 000000 00000160
Defined in Statement: 79.70.7.1.2
[+][-] ASM000048 OFFSET [Code] 00001 00001 00000 000000 00000164
Defined in Statement: 79.70.8.1.2
[+][-] ASM000049 OFFSET [Code] 00001 00001 00000 000000 00000190
Defined in Statement: 79.75.3.1
[+][-] ASM000050 OFFSET [Code] 00001 00001 00000 000000 00000190
Defined in Statement: 79.75.3.2
Referenced in Statement: 79.75.11.1
[+][-] ASM000051 OFFSET [Code] 00001 00001 00000 000000 000001B0
Defined in Statement: 79.75.11.2
Referenced in Statement: 79.75.7.1.1.1
[+][-] ASM000052 OFFSET [Code] 00001 00001 00000 000000 0000019C
Defined in Statement: 79.75.6.1.2
[+][-] ASM000053 OFFSET [Code] 00001 00001 00000 000000 000001A0
Defined in Statement: 79.75.7.1.2
[+][-] ASM000054 OFFSET [Code] 00001 00001 00000 000000 000001A4
Defined in Statement: 79.75.8.1.2
[+][-] CODE OFFSET [Code] 00001 00000 00001 000000 00000000
Defined in Statement: 72.1
[+][-] CYCLE ABSOLUTE 00001 00000 00001 000000 00000C00
Defined in Statement: 70.191
[+][-] CYCLEH ABSOLUTE 00001 00000 00001 000000 00000C80
Defined in Statement: 70.194
[+][-] DVASMSORTSTRING dvasmsortstring OBJECT GLOBAL OFFSET [Code] 00008 00008 00000 000000 00000000
Defined in Statement: 76.2
Referenced in Statement: 76.1
[+][-] ELF_SHF_ALLOC ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 70.1.13
Referenced in Statement: 72.1
[+][-] ELF_SHF_EXECINSTR ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 70.1.14
Referenced in Statement: 72.1
[+][-] ELF_SHF_WRITE ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.1.12
[+][-] ELF_SHT_NOBITS ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 70.1.10
[+][-] ELF_SHT_NOTE ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 70.1.9
[+][-] ELF_SHT_PROGBITS ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.1.8
Referenced in Statement: 72.1
[+][-] ELF_STB_GLOBAL ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.1.17
[+][-] ELF_STB_LOCAL ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 70.1.16
[+][-] ELF_STB_WEAK ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 70.1.18
[+][-] ELF_STT_FILE ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 70.1.24
[+][-] ELF_STT_FUNC ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 70.1.22
[+][-] ELF_STT_NOTYPE ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 70.1.20
[+][-] ELF_STT_OBJECT ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.1.21
[+][-] ELF_STT_SECTION ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 70.1.23
[+][-] EXIT OFFSET [Code] 00001 00001 00000 000000 000001D0
Defined in Statement: 80.1
[+][-] F0 ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 70.109
[+][-] F1 ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.110
[+][-] F10 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 70.119
[+][-] F11 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 70.120
[+][-] F12 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 70.121
[+][-] F13 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 70.122
[+][-] F14 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 70.123
[+][-] F15 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 70.124
[+][-] F16 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 70.125
[+][-] F17 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 70.126
[+][-] F18 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 70.127
[+][-] F19 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 70.128
[+][-] F2 ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 70.111
[+][-] F20 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 70.129
[+][-] F21 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 70.130
[+][-] F22 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 70.131
[+][-] F23 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 70.132
[+][-] F24 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 70.133
[+][-] F25 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 70.134
[+][-] F26 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 70.135
[+][-] F27 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 70.136
[+][-] F28 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 70.137
[+][-] F29 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 70.138
[+][-] F3 ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 70.112
[+][-] F30 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 70.139
[+][-] F31 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 70.140
[+][-] F4 ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 70.113
[+][-] F5 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 70.114
[+][-] F6 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 70.115
[+][-] F7 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 70.116
[+][-] F8 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 70.117
[+][-] F9 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 70.118
[+][-] FA0 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 70.154
[+][-] FA1 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 70.155
[+][-] FA2 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 70.156
[+][-] FA3 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 70.157
[+][-] FA4 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 70.158
[+][-] FA5 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 70.159
[+][-] FA6 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 70.160
[+][-] FA7 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 70.161
[+][-] FALSE ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 70.1.2
[+][-] FCSR ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 70.190
[+][-] FFLAGS ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.188
[+][-] FRM ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 70.189
[+][-] FS0 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 70.152
[+][-] FS1 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 70.153
[+][-] FS10 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 70.170
[+][-] FS11 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 70.171
[+][-] FS2 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 70.162
[+][-] FS3 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 70.163
[+][-] FS4 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 70.164
[+][-] FS5 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 70.165
[+][-] FS6 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 70.166
[+][-] FS7 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 70.167
[+][-] FS8 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 70.168
[+][-] FS9 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 70.169
[+][-] FT0 ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 70.144
[+][-] FT1 ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.145
[+][-] FT10 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 70.174
[+][-] FT11 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 70.175
[+][-] FT2 ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 70.146
[+][-] FT3 ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 70.147
[+][-] FT4 ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 70.148
[+][-] FT5 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 70.149
[+][-] FT6 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 70.150
[+][-] FT7 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 70.151
[+][-] FT8 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 70.172
[+][-] FT9 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 70.173
[+][-] GP ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 70.77
[+][-] INSTRET ABSOLUTE 00001 00000 00001 000000 00000C02
Defined in Statement: 70.193
[+][-] INSTRETH ABSOLUTE 00001 00000 00001 000000 00000C82
Defined in Statement: 70.196
[+][-] NAPIER FLOAT 00001 00000 00001 000000 2.71828182845904523536028747132.71828182845904523536028747135266249775725
Defined in Statement: 70.1.6
[+][-] NO ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 70.1.4
[+][-] PI FLOAT 00001 00000 00001 000000 3.14159265358979323846264338323.14159265358979323846264338327950288419717
Defined in Statement: 70.1.5
[+][-] R0 ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 70.5
[+][-] R1 ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.6
[+][-] R10 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 70.15
[+][-] R11 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 70.16
[+][-] R12 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 70.17
[+][-] R13 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 70.18
[+][-] R14 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 70.19
[+][-] R15 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 70.20
[+][-] R16 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 70.21
[+][-] R17 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 70.22
[+][-] R18 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 70.23
[+][-] R19 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 70.24
[+][-] R2 ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 70.7
[+][-] R20 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 70.25
[+][-] R21 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 70.26
[+][-] R22 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 70.27
[+][-] R23 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 70.28
[+][-] R24 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 70.29
[+][-] R25 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 70.30
[+][-] R26 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 70.31
[+][-] R27 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 70.32
[+][-] R28 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 70.33
[+][-] R29 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 70.34
[+][-] R3 ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 70.8
[+][-] R30 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 70.35
[+][-] R31 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 70.36
[+][-] R4 ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 70.9
[+][-] R5 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 70.10
[+][-] R6 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 70.11
[+][-] R7 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 70.12
[+][-] R8 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 70.13
[+][-] R9 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 70.14
[+][-] RA ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.75
Referenced in Statement: 80.2
[+][-] RM_DYN ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 70.184
[+][-] RM_RDN ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 70.181
[+][-] RM_RMM ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 70.183
[+][-] RM_RNE ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 70.179
[+][-] RM_RTZ ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.180
[+][-] RM_RUP ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 70.182
[+][-] S0 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 70.82
[+][-] S1 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 70.83
[+][-] S10 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 70.100
[+][-] S11 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 70.101
[+][-] S2 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 70.92
[+][-] S3 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 70.93
[+][-] S4 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 70.94
[+][-] S5 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 70.95
[+][-] S6 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 70.96
[+][-] S7 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 70.97
[+][-] S8 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 70.98
[+][-] S9 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 70.99
[+][-] SP ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 70.76
[+][-] T0 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 70.79
Referenced in Statement: 79.20
Referenced in Statement: 79.32.2.1.1
Referenced in Statement: 79.34.1.1
Referenced in Statement: 79.46.3.1.1
Referenced in Statement: 79.52
Referenced in Statement: 79.54.2.1.1
Referenced in Statement: 79.57
Referenced in Statement: 79.59
Referenced in Statement: 79.65.2.1.1
Referenced in Statement: 79.67.1.1
Referenced in Statement: 79.78.3.1.1
Referenced in Statement: 79.80.1
Referenced in Statement: 79.80.2.1.1
[+][-] T1 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 70.80
Referenced in Statement: 79.22
Referenced in Statement: 79.25.2.1.1
Referenced in Statement: 79.26
Referenced in Statement: 79.27.1
Referenced in Statement: 79.48.1
Referenced in Statement: 79.48.3.1.1
Referenced in Statement: 79.56
Referenced in Statement: 79.60.1
[+][-] T2 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 70.81
Referenced in Statement: 79.26
Referenced in Statement: 79.38.2.1
Referenced in Statement: 79.43.2.1
Referenced in Statement: 79.47
Referenced in Statement: 79.57
Referenced in Statement: 79.70.2.1
Referenced in Statement: 79.75.2.1
Referenced in Statement: 79.79
[+][-] T3 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 70.102
Referenced in Statement: 79.19
Referenced in Statement: 79.20
Referenced in Statement: 79.21
Referenced in Statement: 79.22
Referenced in Statement: 79.28
Referenced in Statement: 79.48.2
Referenced in Statement: 79.55
Referenced in Statement: 79.61
[+][-] T4 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 70.103
Referenced in Statement: 79.27.1
Referenced in Statement: 79.39
Referenced in Statement: 79.40
Referenced in Statement: 79.44
Referenced in Statement: 79.45.1
Referenced in Statement: 79.47
Referenced in Statement: 79.60.1
Referenced in Statement: 79.71
Referenced in Statement: 79.72
Referenced in Statement: 79.76
Referenced in Statement: 79.77.1
Referenced in Statement: 79.79
[+][-] T5 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 70.104
Referenced in Statement: 79.28
Referenced in Statement: 79.29
Referenced in Statement: 79.41
Referenced in Statement: 79.42.1
Referenced in Statement: 79.42.2
Referenced in Statement: 79.46.1
Referenced in Statement: 79.46.2
Referenced in Statement: 79.61
Referenced in Statement: 79.62
Referenced in Statement: 79.73
Referenced in Statement: 79.74.1
Referenced in Statement: 79.74.2
Referenced in Statement: 79.78.1
Referenced in Statement: 79.78.2
[+][-] T6 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 70.105
Referenced in Statement: 79.29
Referenced in Statement: 79.32.2.1.1
Referenced in Statement: 79.33
Referenced in Statement: 79.34.1.1
Referenced in Statement: 79.35
Referenced in Statement: 79.40
Referenced in Statement: 79.42.2
Referenced in Statement: 79.45.1
Referenced in Statement: 79.46.2
Referenced in Statement: 79.46.3.1.1
Referenced in Statement: 79.62
Referenced in Statement: 79.65.2.1.1
Referenced in Statement: 79.66
Referenced in Statement: 79.67.1.1
Referenced in Statement: 79.68
Referenced in Statement: 79.72
Referenced in Statement: 79.74.2
Referenced in Statement: 79.77.1
Referenced in Statement: 79.78.2
Referenced in Statement: 79.78.3.1.1
[+][-] TIME ABSOLUTE 00001 00000 00001 000000 00000C01
Defined in Statement: 70.192
[+][-] TIMEH ABSOLUTE 00001 00000 00001 000000 00000C81
Defined in Statement: 70.195
[+][-] TP ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 70.78
[+][-] TRUE ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.1.1
[+][-] X0 ABSOLUTE 00001 00000 00001 000000 00000000
Defined in Statement: 70.40
[+][-] X1 ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.41
[+][-] X10 ABSOLUTE 00001 00000 00001 000000 0000000A
Defined in Statement: 70.50
[+][-] X11 ABSOLUTE 00001 00000 00001 000000 0000000B
Defined in Statement: 70.51
[+][-] X12 ABSOLUTE 00001 00000 00001 000000 0000000C
Defined in Statement: 70.52
[+][-] X13 ABSOLUTE 00001 00000 00001 000000 0000000D
Defined in Statement: 70.53
[+][-] X14 ABSOLUTE 00001 00000 00001 000000 0000000E
Defined in Statement: 70.54
[+][-] X15 ABSOLUTE 00001 00000 00001 000000 0000000F
Defined in Statement: 70.55
[+][-] X16 ABSOLUTE 00001 00000 00001 000000 00000010
Defined in Statement: 70.56
[+][-] X17 ABSOLUTE 00001 00000 00001 000000 00000011
Defined in Statement: 70.57
[+][-] X18 ABSOLUTE 00001 00000 00001 000000 00000012
Defined in Statement: 70.58
[+][-] X19 ABSOLUTE 00001 00000 00001 000000 00000013
Defined in Statement: 70.59
[+][-] X2 ABSOLUTE 00001 00000 00001 000000 00000002
Defined in Statement: 70.42
[+][-] X20 ABSOLUTE 00001 00000 00001 000000 00000014
Defined in Statement: 70.60
[+][-] X21 ABSOLUTE 00001 00000 00001 000000 00000015
Defined in Statement: 70.61
[+][-] X22 ABSOLUTE 00001 00000 00001 000000 00000016
Defined in Statement: 70.62
[+][-] X23 ABSOLUTE 00001 00000 00001 000000 00000017
Defined in Statement: 70.63
[+][-] X24 ABSOLUTE 00001 00000 00001 000000 00000018
Defined in Statement: 70.64
[+][-] X25 ABSOLUTE 00001 00000 00001 000000 00000019
Defined in Statement: 70.65
[+][-] X26 ABSOLUTE 00001 00000 00001 000000 0000001A
Defined in Statement: 70.66
[+][-] X27 ABSOLUTE 00001 00000 00001 000000 0000001B
Defined in Statement: 70.67
[+][-] X28 ABSOLUTE 00001 00000 00001 000000 0000001C
Defined in Statement: 70.68
[+][-] X29 ABSOLUTE 00001 00000 00001 000000 0000001D
Defined in Statement: 70.69
[+][-] X3 ABSOLUTE 00001 00000 00001 000000 00000003
Defined in Statement: 70.43
[+][-] X30 ABSOLUTE 00001 00000 00001 000000 0000001E
Defined in Statement: 70.70
[+][-] X31 ABSOLUTE 00001 00000 00001 000000 0000001F
Defined in Statement: 70.71
[+][-] X4 ABSOLUTE 00001 00000 00001 000000 00000004
Defined in Statement: 70.44
[+][-] X5 ABSOLUTE 00001 00000 00001 000000 00000005
Defined in Statement: 70.45
[+][-] X6 ABSOLUTE 00001 00000 00001 000000 00000006
Defined in Statement: 70.46
[+][-] X7 ABSOLUTE 00001 00000 00001 000000 00000007
Defined in Statement: 70.47
[+][-] X8 ABSOLUTE 00001 00000 00001 000000 00000008
Defined in Statement: 70.48
[+][-] X9 ABSOLUTE 00001 00000 00001 000000 00000009
Defined in Statement: 70.49
[+][-] YES ABSOLUTE 00001 00000 00001 000000 00000001
Defined in Statement: 70.1.3
----- End of DVASM listing -----
CopyRight Roberti & Parau Enterprises, Inc. 2021
This work is licensed under the Creative Commons Attribution-NoDerivatives 4.0 International License.
To view a copy of this license, visit http://creativecommons.org/licenses/by-nd/4.0
or send a letter to Creative Commons, PO Box 1866, Mountain View, CA 94042, USA.
DVASM™ is a trademark of Roberti & Parau Enterprises, Inc.